Abstract: A storage system and method for token provisioning for faster data access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from a host to write data in the memory; write the data in the memory at a starting physical address; provide the host with a token indicating the starting physical address; receive a read command and the token from the host; and read the data stored in the memory at the starting physical address as indicated by the token. Other embodiments are provided.

Abstract: A storage device is provided including a memory controller having a neural processing unit (NPU); a first nonvolatile memory (NVM) connected to the memory controller through a first channel; and a second NVM connected to the memory controller through a second channel. The first NVM stores first weight data for the NPU and the second stores second weight data for the NPU. The memory controller is configured to determine one of the first and second channels that is less frequently accessed upon receiving an inference request from the neural processor, and access a corresponding one of the first weight data and the second weight data using the determined one channel.

Abstract: A system for tracking memory access patterns to be used in making data placement and migration policies. The system includes a processing unit and a system memory. The system memory includes a local memory and a remote memory, each of which having mapped thereon, a plurality of memory pages. Each of the plurality of memory pages corresponds to one or more physical addresses. A set of attributes for each memory page is stored in a physical attribute table (PAT). The PAT is looked up and the attributes updated when a memory access is detected. Attributes stored in the PAT are used to control the movement of memory pages between the local memory and the remote memory. When the attributes in the PAT indicate a remote memory page is being accessed frequently by the processing unit, the remote memory page is moved from the remote memory to the local memory.

Abstract: A controller includes: a host interface providing a host with reception ready signals corresponding to a threshold value in response to a program command; and a processor performing a training operation to determine an optimal value for the threshold value, wherein the processor includes: an outstanding ready-to-transfer (RTT) value selector selecting one value in a range from a minimum value to a maximum value as the threshold value; a time measurer providing the host with the reception ready signals that are selected corresponding to the threshold value and measuring a reception time of data corresponding to each of the selected reception ready signals; a normalizer normalizing the reception times to generate normalized times that are measured for values ranging from the minimum value to the maximum value; and an optimal outstanding RTT value determiner determining the threshold value corresponding to a minimum normalization time as the optimal value.

Abstract: The present invention provides a memory controller configured to access a plurality of channels, wherein each of the channels includes a plurality flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is configured to generate commands with corresponding physical addresses of at least one of the channels. The plurality of control modules are connected to the plurality of channels, respectively, and each of the control modules operates independently to receive the corresponding command with the corresponding physical address from the flash translation layer, to access the flash memory chips within the corresponding channels.

Abstract: Disk access event control for mapped nodes of a cluster storage system supporting a redundant array of independent nodes (mapped RAIN) system is disclosed. A mapped RAIN cluster can be allocated on top of one or more real data clusters. In an embodiment, disk access events can be routed via a storage service instance supporting a mapped node. In another embodiment, disk access events can be routed via another storage service instance that does not support the mapped node. Routing the disk access event via another storage service instance that does not support the mapped node can reduce the use of computing resources. Further, the routing of the disk access event can be according to a proportional disk operation value determined based on historical disk access event characteristics.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes blocks. The controller controls the nonvolatile memory. The controller acquires a write amount to the nonvolatile memory in a first period. The controller calculates an estimated amount of writing to the nonvolatile memory in the first period. The controller changes, when the write amount is larger than the estimated amount by a first threshold value or more, one or more parameters used for writing of data to the nonvolatile memory.

Abstract: A storage device includes a nonvolatile memory; a controller configured to control a write operation of the nonvolatile memory according to a write request received from a host and transmit a response to the write request to the host; and write buffers configured to store write data received with the write request. The controller is further configured to: set a response transmission delay time based on an available size of the write buffers, a minimum response transmission delay time, and a maximum response transmission delay time, transmit the response to the write request to the host after the response transmission delay time passes, and dynamically adjust, as the available size of the write buffers changes, the response transmission delay time within a range from the minimum response transmission delay time to the maximum response transmission delay time.

Abstract: The present disclosure includes apparatuses and methods for command queuing. A number of embodiments include receiving a queued command request at a memory system from a host, sending a command response from the memory system to the host that indicates the memory system is ready to receive a command in a command queue of the memory system, and receiving, in response to sending the command response, a command descriptor block for the command at the memory system from the host.

Abstract: Various embodiments described herein provide for performing inversion refresh of a physical memory location of a memory device (e.g., memory cell on a negative-and (NAND)-type memory device) based on a state of the physical memory location. For some embodiments, the inversion refresh is performed as part of performing garbage collection or reclamation of physical memory locations of a memory device.

Abstract: The present disclosure provides a management method and an apparatus for coexisting multi-storage mediums. The method includes: scanning a plurality of storage mediums to identify the storage medium operating in an online mode; configuring the storage medium operating in the online mode as a first storage medium; establishing a doubly linked list by a controller, wherein the doubly linked list records storage mediums operating in the online mode; determining whether the first storage medium is in a register table; turning on a switching mode of the first storage medium upon determining the first storage medium is in the register table; and retrieving a switching command via a storage layer, wherein the switching command is generated by the controller in response to user request.

Abstract: According to one embodiment, an electronic apparatus includes an interface circuit connectable to a first signal line, a second signal line, and a third signal line, and a controller. Before transmitting data using the first signal line, the controller is configured to transmit a first command using the first signal line while transmitting a first control signal using the second signal line, and transmit a first address using the first signal line while transmitting a second control signal using the third signal line. While transmitting the data using the first signal line, the controller is configured to transmit at least one of a second command and a second address using the second signal line and the third signal line.

Abstract: Aspects of a storage device are provided which reduce write amplification by minimizing data flushes from cache to SLC blocks during RMW operations. A memory of the storage device includes a first memory location of one or more single-level cells and a second memory location of one or more multiple-level cells. A controller of the storage device receives first data associated with a first range of logical addresses and second data associated with a second range of logical addresses. During a RMW operation of the first data, the controller determines whether the first range overlaps with the second range, and stores or flushes the second data in the first memory location when an overlap is determined. The controller stores or writes the second data in the second memory location when an overlap is not determined. Accordingly, data flushing to the single-level cells is minimized when no overlap is determined.

Abstract: A processing-in-memory (PIM) device includes a plurality of memory banks and a plurality of multiplication/accumulation (MAC) operators. The MAC operators perform MAC arithmetic operations using data output from the plurality of memory banks and input into the MAC operators. A page is allocated to have a first page size in the plurality of memory banks in a memory mode. The page is allocated to have a second page size, which is greater than the first page size, in the plurality of memory banks in a MAC arithmetic mode.

Abstract: A memory system includes a memory device configured to store data, and a memory controller configured to perform communication between a host and the memory device and to control the memory device such that, during an operation of programming sequential data, a hash value is generated from logical block addresses of a memory area, to which the sequential data is to be written, and the hash value is stored and such that, during an operation of reading the sequential data, the sequential data is read from the memory area based on the hash value.

Abstract: Providing concurrent access to a tape volume of a tape emulation unit includes a first process generating a first attachment request to attach to the tape emulation unit, generating a first unique id corresponding to the first attachment request, a second process generating a second attachment request, different from the first attachment request, to attach to the tape emulation unit, generating a second unique id corresponding to the second attachment request, and allowing the first process to access a tape volume on the tape emulation unit using the first unique id while the second process concurrently accesses the tape volume on the tape emulation unit using the second unique id. The first process may access the tape volume for writing data to the tape volume. Only one of the processes may access the tape volume for writing data to the tape volume.

Abstract: The invention introduces an apparatus for handling flash physical-resource sets, at least including a random access memory (RAM), a processing unit and an address conversion circuit. The RAM includes multiple segments of temporary space and each segment thereof stores variables associated with a specific flash physical-resource set. The processing unit accesses user data of a flash physical-resource set when executing program code of a Flash Translation Layer (FTL). The address conversion circuit receives a memory address issued from the FTL, converts the memory address into a relative address of one segment of temporary space associated with the flash physical-resource set and outputs the relative address to the RAM for accessing a variable of the associated segment of temporary space.

Abstract: A data storage device may include: a nonvolatile memory configured to store L2P (Logical to Physical) map data and user data; and a controller configured to determine whether read commands which are sequentially transferred from a host device correspond to a backward sequential read, increase a backward sequential read count when the read commands are backward sequential read, set a pre-read start logical block address (LBA) and a length according to a preset condition, when the backward sequential read count is equal to or greater than a reference value, and load an L2P map of the corresponding LBA and user data corresponding to the L2P map from the nonvolatile memory in advance.

Abstract: In some embodiments, an interface of a content management system manages synchronized content on storage systems. For example, the interface stores, on a metadata storage structure, records of metadata associated with blocks of data stored on a storage, the records including block identifiers that uniquely identify the blocks and timestamps associated with the blocks. The interface identifies a batch of storage operations associated with the blocks, including one or more delete operations. For each delete operation, the interface queries the metadata storage structure for a timestamp corresponding to a block of data associated with the delete operation, determines whether the delete operation creates a race condition between the delete operation and an add operation associated with the block of data, and rejects the delete operation when the delete operation creates the race condition or the timestamp corresponding to the block of data is newer than a predetermined period of time.

Abstract: A storage system and method for using proactive device timeout information are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a command from a host; determine whether the command can be executed within a time-out window; and in response to determining that the command cannot be executed within the time-out window, send a request to the host to extend the time-out window. Other embodiments are provided.