Abstract: Efficiently generating effective address translations for memory management test cases including obtaining a first set of EAs, wherein each EA comprises an effective segment ID and a page, wherein each effective segment ID of each EA in the first set of EAs is mapped to a same first effective segment; obtaining a set of virtual address corresponding to the first set of EAs; translating the first set of EAs by applying a hash function to each virtual address in the set of virtual addresses to obtain a first set of PTEG addresses mapped to a first set of PTEGs; and generating a translation for a second set of EAs to obtain a second set of PTEG addresses mapped to the first set of PTEGs.

Abstract: A storage system and method for performing high-speed read and write operations are disclosed. In general, these embodiments discuss ways for performing a fast read in response to determining that the fast read will probably not have a negative impact on performance due to error correction and performing a fast write in response to determining that a storage system criterion is satisfied.

Abstract: An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups.

Abstract: A method operating a memory system, can be provided by reading a plurality of data words from a memory system, where each of the plurality of data words is stored in the memory system in a first dimension-major order. The plurality of data words can be shifted into a transpose memory system in the first dimension in parallel with one another using first directly time adjacent clock edges to store a plurality of transposed data words in a second dimension-major order in the transpose memory system relative to the memory system. The plurality of transposed data words can be shifted out of the transpose memory system in the second dimension using second directly time adjacent clock edges.

Abstract: According to one general aspect, an apparatus may include a first cache configured to store data. The apparatus may include a second cache configured to, in response to a fill request, supply the first cache with data, and an incoming fill signal. The apparatus may also include an execution circuit configured to, via a load request, retrieve data from the first cache. The first cache may be configured to: derive, from the incoming fill signal, address and timing information associated with the fill request, and based, at least partially, upon the address and timing information, schedule the load request to attempt to avoid a load-fill conflict.

Abstract: Embodiments of the present application relate to a method for scheduling virtual disk input and output (I/O) ports, a device for scheduling virtual disk I/O ports, and a computer program product for scheduling virtual disk I/O ports. A method for scheduling virtual disk I/O ports is provided. The method includes assigning a set of service quality ratings to a corresponding set of virtual disk I/O ports based on a set of reading-writing bandwidth quotas associated with the corresponding set of virtual disk I/O ports in a physical machine, determining a total forecast value of a data bandwidth to be used by reading-writing requests and determining virtual disk I/O ports, allocating reading-writing bandwidth limits to the virtual disk I/O ports, and scheduling virtual disk I/O ports on the physical machine.

Abstract: A system for monitoring and reporting data storage status of one or more line replaceable units installed in an aircraft. A data storage monitor onboard the vehicle is in communication with each of the line replaceable units. A storage status is reported, and a storage status log is generated for each line replaceable unit. The storage status logs are communicated to a base station over a communication link established between the base station and the data storage monitor for storage within a repository. The base station has a status log aggregator that generates a report from the storage status logs, an interface for an external management application to access the storage status logs, and an alarm that generates notifications to a predefined destination based upon an evaluation of the storage status logs against one or more alert rules.

Abstract: Data protection compliance between virtual machines' storage policies and backup policies is described. A compliance tool identifies a storage policy associated with a virtual machine storage management tool and a virtual machine. The compliance tool identifies a backup policy associated with the virtual machine. If the compliance tool determines that the backup policy has a data protection capability that is missing from the storage policy, the compliance tool outputs a report which indicates that the backup policy has the data protection capability that is missing from the storage policy.

Abstract: A memory system includes N core dies (N: an integer greater than one) stacked in a vertical direction and including N respective memory circuits having a same structure, a control circuit configured to supply N write data to the N respective memory circuits, an address generating circuit configured to generate a single common address as write addresses at which the N write data are to be stored in the N respective memory circuits, and an address conversion circuit configured to convert the single common address to generate N addresses which are different for the N respective memory circuits and to supply the N addresses as write addresses to the N respective memory circuits.

Abstract: Graphics processing systems and methods are described. For example, one embodiment of a graphics processing apparatus comprises a graphics processing unit (GPU), the GPU including an on-die cache and a cache configuration circuitry to dynamically configure the on-die cache for a plurality of contexts executed by the GPU. The cache configuration block is to receive a cache configuration request, the cache configuration request including context-specific cache requirements for a new context, and determine a priority associated with the context-specific cache requirements. The CCB can compare the context-specific cache requirements with pre-existing cache requirements based on the priority, and reallocate the cache based on the context-specific cache requirements and the priority.

Abstract: An access request processing method and apparatus, and a computer system is disclosed. The computer system includes a processor and a non-volatile memory (NVM). When receiving a write request, the processor determines an object cache page according to the write request. After determining that the NVM stores a log chain of the object cache page, the processor inserts, into the log chain of the object cache page, a second data node recording information about a second log data chunk. The log chain already includes a first data node recording information about the first log data chunk. The second log data chunk is at least partial to-be-written data of the write request. Then, the processor sets, in the first data node, data that is in the first log data chunk and that overlaps the second log data chunk to invalid data.

Abstract: A processor device is provided with hardware-implemented logic to receive an instruction including a pointer identifier and a pointer change value, the pointer identifier including a pointer address field encoded with an address of a line of memory corresponding to a location of a pointer of a particular one of the one or more cyclic buffers, one or more cushion bits, and a buffer identifier field encoded with a buffer identifier assigned to the particular cyclic buffer. The logic further enables the processor to identify that the instruction is to apply to the particular cyclic buffer based on the buffer identifier, determine that the pointer change value causes a wraparound of the pointer in the particular cyclic buffer, and fix location of the pointer in the particular cyclic buffer based on the wraparound.

Abstract: Techniques to facilitate enhanced addressing of local and network resources from a computing system are provided herein. In one implementation, a method of configuring an object memory management unit (OMMU) for a computing system includes transferring a request to at least one network configuration resource for OMMU configuration information, and receiving the OMMU configuration information from the at least one network resource. The method further comprises, based on the OMMU configuration information, generating a mapping of virtual addresses in the computing system to local addresses that address local resource of the computing system and network addresses that address network resources external to the computing system over at least a network.

Abstract: An apparatus for auto addressing includes a communication bus interface configured to receive an address assignment request to assign an address to the apparatus. A functional connection is configured to activate a device connected to the apparatus. A detector is configured to measure a characteristic of the device and to compare the characteristic with a validation parameter. The characteristic depends on the functional connection. An address assignment circuit is configured to store the address in a memory of the apparatus in response to receiving the address assignment request at the apparatus, and the characteristic being validated with the validation parameter.

Abstract: In one example method, one or more source storages and the number of available streams for each source storage are identified, and one or more target storages and the number of available streams for each target storage are also identified. The source storages and target storages are then sorted on the basis of their respective available streams. A comparison is performed of the available source storage streams with available target storage streams, and parallel cloning sessions are created based on the result of the comparison.

Abstract: Representative embodiments disclosed compress expressions so they utilize less physical storage. An expression is placed in a standard representation, such as an expression tree. The system utilizes one or more rules to identify portions of the expression that are likely to be common to other expressions. The common portions are extracted from the expression tree as a template and the remaining portions are hoisted from the expression as unique portions. If the template does not already reside in a cache, the template is stored in the cache. A cache reference is obtained for the template and combined with the unique portions to create a bundle that reduces storage requirements for the expression. The original expression is recovered by retrieving the template from the cache using the cache reference and placing the hoisted unique portions into their original locations in the template.

Abstract: A storage layer may be configured to over-provision logical storage resources to objects. The storage layer may provision the resources in response to, inter alia, a request to open and/or create a zero-length file. The storage layer may be further configured to store data of the objects in a contextual format configured to associate the data with respective logical identifiers. The storage layer may determine an actual, storage size of the object based on the associations stored on the stored associations. Storage clients may rely on the storage layer to determine the size of the object and, as such, may defer and/or eliminate updates to persistent metadata.

Abstract: Synchronization of data layouts and resource utilizations at one or more remote replica sites with the workload and data access statistics at the primary site allows for an efficient and effective workload support transfer in the event of site failover from a primary site to a remote site. Relevant data access information about workload being supported at the primary site is monitored and access pattern information is generated that provides relevant information about frequency and/or rate of access of data on the primary site. The access pattern information is generated and transmitted by a host and/application running on the host. The access pattern information is exported and imported to enable independent decisions to be made a remote site, storing replicated data from the primary site, on how best to utilize its available resources to match the performance requirements currently being supported by the primary site.

Abstract: A SSD caching system for hybrid storages is disclosed. The caching system for hybrid storages includes: a Solid State Drive (SSD) for storing cached data, separated into a Repeated Pattern Cache (RPC) area and a Dynamical Replaceable Cache (DRC) area; and a caching managing module, including: an Input/output (I/O) profiling unit, for detecting I/O requests for accesses of blocks in a Hard Disk Drive (HDD) during a number of continuously detecting time intervals, and storing first data corresponding to first blocks being repeatedly accessed at least twice in individual continuously detecting time intervals to the RPC area sequentially; and a hot data searching unit, for detecting I/O requests for accesses of a HDD during a independently detecting time interval, and storing second data corresponding to second blocks being accessed at least twice in the independently detecting time interval to the DRC area sequentially.

Abstract: An apparatus and method are provided for accessing an address translation cache. The address translation cache has a plurality of entries, where each entry is used to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. The virtual address is generated from a plurality of source values. Allocation circuitry is responsive to received address translation data, to allocate an entry within the address translation cache to store the received address translation data. A hash value indication is associated with the allocated entry, where the hash value indication is computed from the plurality of source values used to generate a virtual address associated with the received address translation data.