Patents Examined by Kalpit Parikh
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Patent number: 10861554Abstract: A memory system includes an array of non-volatile memory cells and a memory controller having a first port to receive a program command that addresses a number of the memory cells for a programming operation, having a second port coupled to the memory array via a command pipeline, and configured to create a plurality of fractional program commands in response to the program command. Execution of each fractional program command applies a single program pulse to the addressed memory cells to incrementally program the addressed memory cells with program data, where the duration of the program pulse associated with each fractional program command is a selected fraction of the total programming time typically required to program the memory cells.Type: GrantFiled: April 18, 2018Date of Patent: December 8, 2020Assignee: Rambus Inc.Inventors: Brent S. Haukness, Ian Shaeffer, Gary Bela Bronner
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Patent number: 10860476Abstract: State information indicates wear levels of respective storage devices and free spaces in the respective storage devices. In response to receiving a request for allocating storage space to the storage system from the storage resource pool, corresponding available spaces in the respective storage devices are determined on the basis of the wear level and the free spaces of the respective storage devices, here the corresponding available spaces represent storage spaces in the respective storage devices which are allocatable to the storage system. A group of storage devices are selected from a plurality of storage devices on the basis of the corresponding available spaces. Requested storage spaces are allocated to the storage system from available spaces in the group of storage devices. Thereby, wear levels of various storage devices in the resource pool may be balanced, and further the overall life of the resource pool may be prolonged.Type: GrantFiled: November 26, 2018Date of Patent: December 8, 2020Assignee: EMC IP Holding Company LLCInventors: Xinlei Xu, Jian Gao, Changyu Feng, Haiying Tang, Ruiyong Jia
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Patent number: 10853259Abstract: A system and method of exitless extended page table switching includes a nested hypervisor writing pointer addresses to an extended page table list, where each pointer address is associated with an extended page table. The host hypervisor verifies that each pointer address corresponds to a guest physical address for one of the extended page tables. The host hypervisor then creates shadow extended page tables, each of which includes a shadow pointer address corresponding to a host physical address, writes, in a local page table list, each shadow pointer address and an index of each shadow extended page table, and loads the local page table list. The nested guest requests to switch between two extended page tables. The nested guest then identifies a matching entry for an extended page table in the local page table list and switches to the extended page table without triggering an exit.Type: GrantFiled: December 29, 2017Date of Patent: December 1, 2020Assignee: RED HAT, INC.Inventor: Bandan Das
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Patent number: 10846011Abstract: A method includes identifying, by a host computing device hosting a virtual machine, a plurality of disk volumes of a virtual disk stored on a first storage device, wherein the disk volumes are arranged in a hierarchical order. The method further includes determining, by the host computing device, a block that is present in a first disk volume and a second disk volume of the plurality of disk volumes, wherein the second disk volume is at a higher level in the hierarchical order than the first disk volume. The method also includes copying, by the host computing device, data from the block stored on the first storage device to a backup disk volume residing on a second storage device and removing the block on the first storage device.Type: GrantFiled: August 29, 2018Date of Patent: November 24, 2020Assignee: Red Hat Israel, Ltd.Inventors: Maor Lipchuk, Arik Hadas
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Patent number: 10838855Abstract: This storage system has one or more non-volatile memory devices and a processor unit that comprises one or more processors connected to the one or more non-volatile memory devices. At least a portion of the non-volatile memory of each of the one or more non-volatile memory devices comprises a user area, which is a storage area to which data is written, and an update area, which is a storage area to which update data for the original data is written. The processor unit changes the user capacity, namely the capacity of the user area, of each of the one or more non-volatile memory devices on the basis of at least one of one or more resource usage rates of the one or more non-volatile memory devices.Type: GrantFiled: February 20, 2017Date of Patent: November 17, 2020Assignee: HITACHI, LTD.Inventors: Naoya Machida, Shigeo Homma
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Patent number: 10832728Abstract: Systems for location selection based on adjacent location errors are provided. One system includes a monitor module that monitors write numbers for one or more locations on a storage device, wherein a write number in the write numbers describes a number of times a storage device operation has been performed at a location in the one or more locations. Additionally, the system includes an identification module that identifies locations in one or more locations that are susceptible to adjacent location errors, wherein an adjacent location error is an error caused by a storage device operation associated with an adjacent location. Also, the system includes a selection module that selects a location in one or more locations for storing data based on monitored write numbers and identified locations.Type: GrantFiled: April 5, 2018Date of Patent: November 10, 2020Assignee: International Business Machines CorporationInventors: Sasikanth Eda, Deepak Ghuge, Poornima Gupte, Sukumar Vankadhara
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Patent number: 10824576Abstract: A multi-streaming memory system includes a memory, and a processor coupled to the memory, the processor executing a software component that is configured to identify multiple attributes that are each related to logical block addresses (LBAs), and that each correspond to each of a plurality of streams of data writes, evaluate an importance factor for each of the attributes for each of the streams, and clustering two or more of the LBAs by assigning a stream ID to each of the LBAs based on all of the importance factors for each of the LBAs and the assigned stream.Type: GrantFiled: March 6, 2019Date of Patent: November 3, 2020Assignee: Samsung Electronics Co., Ltd.Inventors: Janki S. Bhimani, Jingpei Yang, Changho Choi, Jianjian Huo
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Patent number: 10817177Abstract: Disclosed herein are methods and apparatuses related to the use of counter tables. A counter table can comprise a plurality of lower-level counters and an upper-level counter. A range of values capable of being represented by a lower-level counter from the plurality of lower-level counters can be enlarged by associating the lower-level counter with the upper-level counter. A counter table can be associated with a network device.Type: GrantFiled: February 22, 2019Date of Patent: October 27, 2020Assignee: Amazon Technologies, Inc.Inventors: Thomas A. Volpe, Mark Anthony Banse
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Patent number: 10802731Abstract: Described is storage system and method for reducing power consumption. The storage system has first and second physical disks configured to provide mirroring. The first physical disk is placed into a power-saving mode of operation, while the second physical disk is in an active mode of operation responding to read and write requests. The first physical disk transitions from the power-saving mode of operation to an active mode of operation for destaging writes pending from cache to the first physical disk, while the second physical disk responds to read and write requests. The second physical disk transitions from the active mode of operation to the power-saving mode of operation, while the first physical disk responds to read and write requests.Type: GrantFiled: January 28, 2019Date of Patent: October 13, 2020Assignee: EMC IP HOLDING COMPANY LLCInventors: Adnan Sahin, Sachin More, Preston Crow, Ron Arnan
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Patent number: 10802727Abstract: A system and method of implementing distributed metadata checkpointing in a storage device. A storage device is disclosed that includes storage device that employs distributed metadata checkpointing, including: flash memory; and a controller that collects metadata checkpoints and includes: a checkpoint partitioner that partitions a metadata checkpoint into a set of segments; and a segment loader that stores each segment of the set of segments into a spare region of a corresponding different flash memory pages during a write operation of data to flash memory.Type: GrantFiled: May 21, 2018Date of Patent: October 13, 2020Assignee: SCALEFLUX, INC.Inventors: Qi Wu, Duy Nguyen, Wenzhong Wu, Jiangpeng Li, Yong Peng
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Patent number: 10797723Abstract: A technique for selecting context models (CMs) for a CM ensemble (CME) in a context mixing compressor includes measuring compression ratios (CRs) of the compressor on a dataset for each CM included in a base set of CMs. A first CM that has a maximum CR for the dataset is added to the CME. In response to a desired number of the CMs not being in the CME, subsequent CRs for the compressor are measured on the dataset for each of the CMs in the base set of CMs that are not in the CME in conjunction with one or more CMs in the CME. In response to a desired number of the CMs not being in the CME, subsequent CMs that in conjunction with the one or more CMs in the CME result in a maximum subsequent CR for the dataset are added to the CME.Type: GrantFiled: March 14, 2017Date of Patent: October 6, 2020Assignee: International Business Machines CorporationInventors: Tobias Blaettler, Thomas Mittelholzer, Thomas Parnell, Charalampos Pozidis
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Patent number: 10789162Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of blocks and a controller. The controller manages a garbage collection count for each of blocks containing data written by a host, the garbage collection count indicating the number of times the data in said each of the blocks has been copied by a garbage collection operation of the nonvolatile memory. The controller selects, as garbage collection target blocks, first blocks associated with a same garbage collection count. The controller copies valid data in the first blocks to a copy destination free block. The controller sets, as a garbage collection count of the copy destination free block, a value obtained by adding one to a garbage collection count of the first blocks.Type: GrantFiled: December 5, 2018Date of Patent: September 29, 2020Assignee: Toshiba Memory CorporationInventor: Shinichi Kanno
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Patent number: 10768821Abstract: There are provided a memory system for processing data and a method for operating the memory system. A memory system includes: a memory device including a plurality of memory blocks for storing data; and a controller for creating a SPOT table including a plurality of SPOT entries according to a logical block address (LBA) of the data and managing the SPOT table, using a least recently used (LRU) algorithm.Type: GrantFiled: April 4, 2018Date of Patent: September 8, 2020Assignee: SK hynix Inc.Inventor: Sung Kwan Hong
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Patent number: 10761731Abstract: Application relates to storage technologies, and in particular, to writing data in a storage system having solid state disks. Embodiments of the application provide an array controller, including a communication interface and a processor. The processor receives information about a logical block from a solid state disk. The information about the logical block includes a size of the logical block and indication information of the logical block, and the logical block includes one or more physical blocks. The processor sends multiple write data requests to the solid state disk. Each write data request includes data, and each write data request instructs the solid state disk to write the data into the logical block indicated by the indication information of the logical block. A total size of data included in the multiple write data requests is equivalent to the size of the logical block.Type: GrantFiled: February 6, 2018Date of Patent: September 1, 2020Assignee: HUAWEI TECHNOLOGIES CO., LTD.Inventors: Peijun Jiang, Qiang Xue, Keji Huang
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Patent number: 10739995Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include a flash memory to store data and support for a number of device streams. The SSD may also include an SSD controller to manage reading data from and writing data to the flash memory. The SSD may also include a host interface logic, which may include a receiver to receive the commands associated with software streams from a host, a timer to time a window, a statistics collector to determine values for at least one criterion for the software streams from the commands, a ranker to rank the software streams according to the values, and a mapper to establish a mapping between the software streams and device streams.Type: GrantFiled: December 13, 2018Date of Patent: August 11, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hingkwan Huen, Changho Choi
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Patent number: 10733232Abstract: A memory system includes a memory device configured to store data, and a memory controller configured to perform communication between a host and the memory device and to control the memory device such that, during an operation of programming sequential data, a hash value is generated from logical block addresses of a memory area, to which the sequential data is to be written, and the hash value is stored and such that, during an operation of reading the sequential data, the sequential data is read from the memory area based on the hash value.Type: GrantFiled: July 10, 2018Date of Patent: August 4, 2020Assignee: SK hynix Inc.Inventor: Dong Sop Lee
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Patent number: 10725782Abstract: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a memory system comprises a memory table providing multiple memory table entries, each including a usefulness indicator. A memory controller of the memory system comprises a global polarity indicator representing how the usefulness indicator for each memory table entry is interpreted and updated by the memory controller. If the global polarity indicator is set, the memory controller interprets a value of each usefulness indicator as directly corresponding to the usefulness of the corresponding memory table entry. Conversely, if the global polarity indicator is not set, the polarity is reversed such that the memory controller interprets the usefulness indicator value as inversely corresponding to the usefulness of the corresponding memory table entry.Type: GrantFiled: September 12, 2017Date of Patent: July 28, 2020Assignee: Qualcomm IncorporatedInventors: Anil Krishna, Yongseok Yi, Eric Rotenberg, Vignyan Reddy Kothinti Naresh, Gregory Michael Wright
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Patent number: 10725668Abstract: A type of data relocation to perform on a group of solid state storage cells is selected from a group that includes garbage collection and wear leveling. Source blocks in the group of solid state storage cells are identified using the selected type of data relocation. The source blocks are read in order to obtain relocated data and the relocated data is stored in an open block in the group of solid state storage cells. Relocated data associated with the selected type of data relocation is stored in the open block and relocated data associated with the unselected type of data relocation is excluded from the open block.Type: GrantFiled: August 3, 2015Date of Patent: July 28, 2020Assignee: SK hynix Inc.Inventors: Xiangyu Tang, Jason Bellorado, Lingqi Zeng, Zheng Wu
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Patent number: 10719439Abstract: A method operable with the storage device includes determining a workload to the storage device based on host Input/Output (I/O) requests to the storage device. When the workload is above a threshold, a first portion of the storage device is selected for garbage collection based on the I/O requests. Otherwise, when the workload is below the threshold, a second different portion of the storage device is selected for garbage collection based on a storage ability of the second portion of the storage device.Type: GrantFiled: September 6, 2017Date of Patent: July 21, 2020Assignee: Seagate Technology LLCInventors: Ryan James Goss, Siddhartha K. Panda, Daniel J. Benjamin, Ryan C. Weidemann
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Patent number: 10713161Abstract: According to one embodiment, a memory system includes a nonvolatile memory, and a controller electrically connected to the nonvolatile memory. The controller receives, from a host, a write command including a logical block address. The controller obtains a total amount of data written to the nonvolatile memory by the host during a time ranging from a last write to the logical block address to a current write to the logical block address, or time data associated with a time elapsing from the last write to the logical block address to the current write to the logical block address. The controller notifies the host of the total amount of data or the time data as a response to the received write command.Type: GrantFiled: March 20, 2019Date of Patent: July 14, 2020Assignee: Toshiba Memory CorporationInventor: Shinichi Kanno