Abstract: In one embodiment, a solid state storage drive comprises a plurality of flash memory devices communicatively coupled to a bus and a channel controller communicatively coupled to the bus, the channel controller comprising an execution time calculator configured to determine an aggregate execution time duration for a sequence of commands in a command execution queue based on a data transfer rate presently assigned for communications over the bus, and a channel execution unit configured to determine when to place a second command in a command execution queue based at least in part on the aggregate execution time duration. In one embodiment, the execution time calculator is further configured to determine the aggregate execution time duration based on the data transfer rate and a data payload quantity associated with at least one command in the sequence of commands.

Abstract: Provided are techniques for handling cache and Non-Volatile Storage (NVS) out of sync writes. At an end of a write for a cache track of a cache node, a cache node uses cache write statistics for the cache track of the cache node and Non-Volatile Storage (NVS) write statistics for a corresponding NVS track of an NVS node to determine that writes to the cache track and to the corresponding NVS track are out of sync. The cache node sets an out of sync indicator in a cache data control block for the cache track. The cache node sends a message to the NVS node to set an out of sync indicator in an NVS data control block for the corresponding NVS track. The cache node sets the cache track as pinned non-retryable due to the write being out of sync and reports possible data loss to error logs.

Abstract: In one embodiment, the method includes sensing, by a memory device, a temperature of the memory device; and generating, by the memory device, a response to a single received command. The response includes temperature information, and the temperature information provides information on the sensed temperature. In one embodiment, the single received command is a read status request command, the read status request command requests status information on the memory device, and the status information includes the temperature information.

Abstract: A technique for operating a data storage system includes accessing respective absolute expiration times for valid pages in one or more candidate storage blocks. Garbage collection is performed on ones of the candidate storage blocks that include a first predetermined number of the valid pages that do not expire, as indicated by the absolute expiration times, prior to a first predetermined time period. Garbage collection is deferred on ones of the candidate storage blocks that include a second predetermined number of the valid pages that expire, as indicated by the absolute expiration times, prior to a second predetermined time period.

Abstract: An embodiment of a semiconductor package apparatus may include technology to track a modification to a processor cache line, and set an indicator to indicate if the modification relates to a transaction. Other embodiments are disclosed and claimed.

Abstract: An LL server (LLS) may process metadata requests for a file system in LL mode in a distributed file storage services (DFSS). For requests that require allocating blocks to file system objects in the backing store, instead of relying on distributed transactions used for file systems in high throughput (HT) mode, a pool of blocks may be pre-allocated for the LL file system in the backing store, and a free block list may be maintained in local memory of the LLS. When a metadata operation requires blocks to be allocated, the blocks are assigned to the respective object from the blocks in the pool. A background process may allocate new blocks in the pool upon the number of blocks dropping below a threshold, or upon block allocation rate for the file system increasing.

Abstract: A system includes a network interface, a processing device, and a memory device. The memory device stores instructions for accessing a first log file of a first format type from a first server and converting the first log file to a first record in a shared data-interchange format. A second log file of a second format type is accessed from a second server. The second log file is converted to a second record in the shared data-interchange format, and instances of the first and second record are collected over a period of time. A resource allocation of the first server and the second server is analyzed based on the instances of the first record and the second record. A resource allocation adjustment request is transmitted to one or more of the server systems based on a predicted trend of the resource allocation of the first and second server.

Abstract: A guarded storage facility sets up a boundary indicating a range of addresses to be guarded or protected. When a program attempts to access an address in a guarded section defined by the boundary, a guarded storage event occurs. Use of this facility facilitates performance of certain tasks within a computing environment, including storage reclamation.

Abstract: A cache coherence system manages both internode and intranode cache coherence in a cluster of nodes. Each node in the cluster of nodes is either a collection of processors running an intranode coherence protocol between themselves, or a single processor. A node comprises a plurality of coherence ordering units (COUs) that are hardware circuits configured to manage intranode coherence of caches within the node and/or internode coherence with caches on other nodes in the cluster. Each node contains one or more directories which tracks the state of cache line entries managed by the particular node. Each node may also contain one or more scoreboards for managing the status of ongoing transactions. The internode cache coherence protocol implemented in the COUs may be used to detect and resolve communications errors, such as dropped message packets between nodes, late message delivery at a node, or node failure.

Abstract: Provided is an electronic apparatus for which an increase in cost due to an increase in the size of the electronic device and an increase in the number of parts is suppressed. A system-control unit manages each of the partitions of a HDD and a SSD (storage device) that has a smaller storage capacity than the HDD by a mounting process. When it becomes impossible to read data from or write data to any one of the partitions, the system-control unit moves data of the other partitions to the SSD (storage device). Moreover, the system-control unit, together with disconnecting the disabled partition, replaces the disabled partition with the partition to which the data is moved.

Abstract: Embodiments of apparatuses, methods, and systems for inter-cluster communication of live-in register values are described. In an embodiment, a processor includes a plurality of execution clusters. The processor also includes a cache memory in which to store a value to be produced by a first execution cluster of the plurality of execution clusters and consumed by a second execution cluster of the plurality of execution clusters. The cache memory is separate from a system memory hierarchy and a register set of the processor.

Abstract: The present invention provides a memory resource management method and apparatus. The method includes: first, determining a recyclable cache unit according to first indication information and second indication information that correspond to each cache unit, where the first indication information and the second indication information both include at least one bit, the first indication information indicates whether the cache unit is occupied, and the second indication information indicates a quantity of cache unit recycling periods for which the cache unit has been occupied; and then, recycling the recyclable cache unit. A quantity of cache unit recycling periods is set, and when a time for which a cache unit has been occupied reaches the preset quantity of cache unit recycling periods, the cache unit is forcibly recycled, thereby effectively improving cache unit utilization and improving system bandwidth utilization.

Abstract: A data processing system for managing at least first and second memories includes a caching manager and a translation lookaside buffer (TLB). The caching manager comprises hardware configured to transfer data between the memories and is configured to monitor accesses to the first memory by a processing device and transfer data in a frequently accessed region at a first address in the first memory to a region at a second address in the second memory. When the data has not been transferred to the second memory, the TLB stores a virtual address and a corresponding address in the first memory. However, when the data has been transferred to the second memory, the TLB stores the virtual address and a corresponding address in the second memory. A mapping between the addresses in the first and second memories may be stored in a shadow-address table.

Abstract: Provided is a linking server that can easily link outputted data with another system. The linking server includes: a communication unit that is capable of communicating between a management server that collects one or more pieces of operating information from one or more image forming apparatus, and an external system that performs processing using the one or more pieces of operating information; a storage unit; an input/output unit that acquires the one or more pieces of operating information that is outputted from the management server, and stores that operating information in the storage unit; and a packaging unit that acquires the one or more pieces of operating information, generates compressed data by performing a compression process and a packaging process, and writes the generated compressed data back into the storage unit; wherein the input/output unit outputs the compressed data to the external system.

Abstract: Apparatus and method for managing data in a hybrid data storage device. The device has a first non-volatile memory (NVM) of solid state memory cells arranged into a first set of garbage collection units (GCUs), and a second NVM as a rotatable data recording medium arranged into a second set of GCUs each comprising a plurality of shingled magnetic recording tracks. A control circuit combines a first group of logical block units (LBUs) stored in the first set of GCUs with a second group of LBUs stored in the second set of GCUs to form a combined group of LBUs arranged in sequential order by logical address. The control circuit streams the combined group of LBUs to a zone of shingled magnetic recording tracks in a selected one of the second set of GCUs. A combined media translation map identifies physical addresses in both the first and second NVMs.

Abstract: A system and method for performing a copyback operation are provided. The disclosed method includes initiating a copyback process to move data from an online data storage drive to a spare data storage drive by setting an indicator in hardware to divert all write completions on the online data storage drive. The method further includes, while the indicator in hardware is set to divert the write completions, incrementing on a per-strip basis a copy of data from the online data storage drive to the spare data storage drive. The method further includes only after all data from the online data storage drive has been copied to the spare data storage drive, changing the setting of the indicator in hardware so that write requests received for the online data storage drive during the copyback process are re-issued on to the spare data storage drive.

Abstract: Devices and techniques for managing partial superblocks in a NAND device are described herein. A set of superblock candidates is calculated. Here, a superblock may have a set of blocks that share a same position in each plane in each die of a NAND array of the NAND device. A set of partial super block candidates is also calculated. A partial superblock candidate is a superblock candidate that has at least one plane that has a bad block. A partial superblock use classification may then be obtained. Superblocks may be established for the NAND device by using members of the set of superblock candidates after removing the set of partial superblock candidates from the set of superblock candidates. Partial superblocks may then be established for classes of data in the NAND device according to the partial superblock use classification.

Abstract: Saving a capacity of an on-premises storage apparatus, a high access performance of the on-premises storage apparatus, and resuming an operation quickly and accurately by using data on a cloud when a resource in the on-premises fails are achieved. A processor provides a first volume which is a virtual volume, and configures a copy pair of the first volume and a second volume provided from another storage system. Write data to the first volume is transferred to the second volume via a network, based on the copy pair. The processor writes to the memory a part of data written to the second volume, and writes to the storage device the data written to the memory.

Abstract: A storage system includes a first storage unit including a first processor and a first array of node modules, each including a memory unit, and a second storage unit including a second processor and a second array of node modules, each including a memory unit. The first processor is configured to control the first and second storage units, and the second processor is configured to control the second storage unit and not the first storage unit when the first processor is set to control the first and second storage units, and control the first and second storage units, when the first processor is set to not control the second storage unit.

Abstract: Efficiently generating effective address translations for memory management test cases including obtaining a first set of EAs, wherein each EA comprises an effective segment ID and a page, wherein each effective segment ID of each EA in the first set of EAs is mapped to a same first effective segment; obtaining a set of virtual address corresponding to the first set of EAs; translating the first set of EAs by applying a hash function to each virtual address in the set of virtual addresses to obtain a first set of PTEG addresses mapped to a first set of PTEGs; and generating a translation for a second set of EAs to obtain a second set of PTEG addresses mapped to the first set of PTEGs.