Abstract: Example systems and methods for integrating a sharded primary data store (e.g., a source-of-truth relational database management system), a secondary data store (e.g., external cache) and an external global index are described. The approach implements a modified read-through/write-through data access pattern that integrates read and write flows in order to support high-concurrency environments while maintaining immediate consistency between all three stores. Writes are handled using a three-phase flow that avoids concurrency-related race conditions and the need to block in the secondary store in order to maintain cross-store consistency. Reads are never dirty and will repair the secondary store as needed, presenting an immediately consistent view of data to application consumers.

Abstract: Scalable control/management data structures enable optimizing performance and/or attempting to achieve a particular performance target of an SSD in accordance with host interfacing, number of NVM devices, NVM characteristics and size, and NVM aging and performance decline. Pre-scaled data structures are included in SSD controller firmware loadable at system initialization. Static data structure configurations enable load-once-operate-for-product-lifetime operation for consumer applications. Dynamic configurations provide sequences of data structures pre-scaled to optimize operation as NVM ages and performance declines. Pre-configured adjustments in data structure size included in consecutive configurations periodically replace earlier configurations at least one time during product lifetime, producing a periodic rescaling of data structure size to track changes in aging NVM.

Abstract: A cache memory system and a caching method for a tile-based rendering may be provided. Each of cache lines in the cache memory system may include delayed-replacement information. The delayed-replacement information may indicate whether texture data referred to at a position of an edge of a tile is included in a cache line. When a cache line corresponding to an access-requested address is absent in the cache memory system, the cache memory system may select and remove a cache line to be removed from an associative cache unit, based on delayed-replacement information.

Abstract: An apparatus includes, in at least one aspect, a memory interface configured to connect with a plurality of multi-level memory cells and a circuitry coupled with the memory interface. The plurality of multi-level memory cells include a first page and a second page. The first page is associated with bits of a first significance. The second page is associated with bits of a second significance. The circuitry is configured to map a first portion of an encoded data sector to the first page and map a second portion of the encoded data sector to the second page. The first portion excludes the second portion and the second portion excludes the first portion such that each of the first page and the second page contains different data from the encoded data sector.

Abstract: A solid state drive (SSD) having a first memory portion comprising SLC flash memory and a second memory portion comprising MLC flash memory. The first memory portion may store read/write data, and the second memory portion may store read-only or read-mostly data. In some instances, the second memory portion may store historical data. The present disclosure also relates to a method of data progression in a hybrid solid state drive having both single-level cell (SLC) flash memory and multi-level cell (MLC) flash memory. The method may include monitoring write operations to the SLC memory, determining whether the frequency of write operations to a particular portion of the SLC memory is below a determined threshold, and moving the data stored in the particular portion of the SLC memory to the MLC memory.

Abstract: Disclosed embodiments are directed to systems and methods for dynamic overprovisioning for data storage systems. In one embodiment, a data storage system can reserve a portion of memory, such as non-volatile solid-state memory, for overprovisioning. Depending on various overprovisioning factors, recovered storage space due to compressing user data can be allocated for storing user data and/or overprovisioning. Utilizing the disclosed dynamic overprovisioning systems and methods can result is more efficient utilization of cache memory, reduction of write amplification, increase in a cache hit rate, and the like. Improved data storage system performance and increased endurance and longevity can thereby be attained.

Abstract: Disclosed is an information processing device provided with: a plurality of processing units each having a TLB (Translation Lookaside Buffer); a means for acquiring a designation of a processing unit, from among the plurality of processing units, where TLB information is to be collected, and for acquiring a designation of the timing at which the TLB information is to be collected; and a means for collecting the TLB information from the designated processing unit at the designated timing.

Abstract: The invention provides an elastic or flexible SSD cache utilizing a hybrid RAID protocol combining RAID-0 protocol for read data and RAID-5 single parity protocol for write data in the same cache array. Read data may be stored in window sized allocations using RAID-0 protocol to avoid allocating an entire RAID stripe for read cache data. In the same SSD volume, dirty write data is stored in row allocations using RAID-5 protocol to provide single parity for the dirty write data. Read data is typically stored a window from the physical device having the largest number of available windows. Write data is stored in a row including the next available window in each arm, which decouples the window structure of the rows from the stripe configuration of the physical memory devices.

Abstract: A method and system enable tape back-up of objects stored to an object storage platform and also enable efficient backup to a secondary storage device data objects. An offline-replica bit within a metadata of an object being stored is set to a first value, indicating that the stored object is available for secondary storage to a second storage device. In response to receiving a request for backup of one or more objects from the object storage platform: the storage controller: identifies which objects have an offline-replica bit value that is the first value; and provides only those objects requested that have their offline-replica bit value equal to the first value. An external backup tracking mechanism identifies which objects have been backed-up to the secondary storage, and only those objects that have not previously been backed up are backed up during a subsequent backup request.

Abstract: Embodiments generally relate to a command protocol and/or related circuits and apparatus for communication between a memory device and a memory controller. In one embodiment, the memory controller includes an interface for transmitting commands to the memory device, wherein the memory device includes bitline multiplexers, and accessing of memory cells within the memory device is carried out by a command protocol sequence that includes a wordline selection, followed by bitline selections by the bitline multiplexers. In another embodiment, a memory device includes bitline multiplexers and further includes an interface for receiving a command protocol sequence that specifies a wordline selection followed by bitline selections by the bitline multiplexers.

Abstract: Providing for a paradigm shift in block-level abstraction for storage devices is described herein. At a block-level, storage is characterized as a variable size data record, rather than a fixed size sector. In some aspects, the variable size data record can comprise a variable binary key-data pair, for addressing and identifying a variable size block of data, and for dynamically specifying the size of such block in terms of data storage. By changing the key or data values, the location, identity or size of block-level storage can be modified. Data records can be passed to and from the storage device to facilitate operational commands over ranges of such records. Block-level data compression, space management and transactional operations are provided, mitigating a need of higher level systems to characterize underlying data storage for implementation of such operations.

Abstract: A method for reducing memory latency in a processor includes identifying an independent instruction (or cache miss instruction) and corresponding dependent instructions from a re-circulating issue window (RIW) when a cache miss is encountered. The cache miss instruction and corresponding dependent instructions are moved to a re-circulating issue buffer (RIB) and moved back to the RIW from the RIB for processing when the cache miss is resolved.

Abstract: Exemplary embodiments provide a management server that controls a storage subsystem based on the cache status on a server. In accordance with one aspect, a system comprises: a storage system operable to couple to a server and to manage a plurality of storage tiers, each of the plurality of storage tiers operable to store data sent from the server; and a management computer operable to manage a storage tier of the plurality of storage tiers for storing data based on whether the data is stored in a cache memory in the server or not.

Abstract: A storage apparatus includes a memory that stores a job management information that registers a write job corresponding to a write command upon receiving the write command from other apparatus, a cache memory that stores data designated as target data by the write command, a storage drive that records the data stored in the cache memory to a storage medium based on the write job registered in the job management information, and a controller that controls a timing to output to the other apparatus a completion report of the write command based on a load condition of the storage device related to an accumulation count of write job acquired from the job management information.

Abstract: In one embodiment, a method for managing access to a fast non-volatile storage device, such as a solid state device, and a slower non-volatile storage device, such as a magnetic hard drive, can include a method of managing a sparse logical volume in which unmapped blocks of the logical volume are not allocated until use. In one embodiment, a method of sparse hole filling operates in which range locks are dynamically adjusted to perform allocations for sparse hole filling, and then re-adjusted to perform standard operations using a byte range lock. In one embodiment, a high level data structure can be used in the range lock service in the form of an ordered search tree, which could use any search tree algorithm, such as red-black tree, AVL tree, splay tree, etc.

Abstract: A request to modify an object in storage that is associated with one or more computing devices may be obtained, the storage organized based on a latch-free B-tree structure. A storage address of the object may be determined, based on accessing a mapping table that includes map indicators mapping logical object identifiers to physical storage addresses. A prepending of a first delta record to a prior object state of the object may be initiated, the first delta record indicating an object modification associated with the obtained request. Installation of a first state change associated with the object modification may be initiated via a first atomic operation on a mapping table entry that indicates the prior object state of the object. For example, the latch-free B-tree structure may include a B-tree like index structure over records as the objects, and logical page identifiers as the logical object identifiers.

Abstract: A virtual capacity acquisition unit acquires a size of virtual capacity of a save data area from an application. A storage capacity acquisition unit acquires a size of save data of the application. A writing control unit prohibits the application from writing the save data exceeding the virtual capacity in a recording device. A free space acquisition unit acquires a size of free space of the recoding device, and the writing control unit prohibits the writing of save data whose size is larger than that of the free space.

Abstract: Provided is a multi-port cache memory apparatus and a method of the multi-port cache memory apparatus. The multi-port memory apparatus may divide an address space into address regions and allocate the divided memory regions to cache banks, thereby preventing the concentration of access to a particular cache.

Abstract: An apparatus for elastic caching of redundant cache data. The apparatus may have a plurality of buffers and a circuit. The circuit may be configured to (i) receive a write request from a host to store write data in a storage volume, (ii) allocate a number of extents in the buffers based upon a redundant organization associated with the write request and (iii) store the write data in the number of extents, where (a) each of the number of extents is located in a different one of the buffers and (b) the number of extents are dynamically linked together in response to the write request.

Abstract: A RAID bad block module is added to a RAID controller. The bad block module intercepts bad block errors and marks them in a bad block table. When a bad block error is intercepted the bad block module logs the error and determines, based on the error and previously received errors logged in the table, whether the RAID controller can handle the error without failing the entire array. If so, the bad block module passes the error to the RAID controller. Else, the bad block module passes the error to an application or operating system where it is handled like any other disk error. Thus, instead of failing the entire array, the bad block errors are dealt with by the operating system.