Abstract: A memory circuit with glitch-less transfer of timing information. In one embodiment, the invention is a memory circuit including a controller, multiple loads, a command link communicatively coupling the controller and the loads and a data link. The data link includes multiple data clocks and communicatively couples the controller and the multiple loads. In another embodiment, the invention transfers data between a memory controller and a RAM by coupling the controller and the RAM using a data bus and multiple clock lines. The invention transfers a read/write command from the controller to the RAM and then transfers data associated with the read/write command, clocking the data using one of the clock lines.

Abstract: A mouse interface converter is provided, which allows a mouse to be connectable to a computer system, such as a personal computer (PC), installed with either an RS-232 serial port or a PS/2 port. This mouse interface converter allows the mouse to be connected directly to PS/2 port and via an adapter to RS-232 serial port. The mouse interface converter includes a mode-detection circuit for detecting which type of port the mouse is currently being connected. The mode-detection circuit can generate a mode-indicating signal indicative of the type of the currently connected port, which is then used to set a control circuit to convert the mouse data to the corresponding format. The mouse interface converter further includes a driving circuit that allows the mouse to be more compatible with various signals of either the PS/2 port or the RS-232 serial port. This feature allows the mouse to be considerably reduced in power consumption that allows the mouse to be suitable for use on notebook computers.

Abstract: An automatically configuring storage array includes a plurality of media storage devices coupled together within a network of devices. Preferably, the network of devices is an IEEE 1394-1995 serial bus network of devices. The media storage devices are utilized to record and retrieve streams of data transmitted within the network of devices. The media storage devices communicate with each other in order to store and retrieve streams of data over multiple media storage devices, if necessary. When a record or playback command is received by any one of the media storage devices, the media storage devices send control communications between themselves to ensure that the stream of data is recorded or transmitted, as appropriate. Control of the record or transmit operation is also transferred between the media storage devices in order to utilize the full capacity of the available media storage devices. Preferably, streams of data are recorded utilizing redundancy techniques.

Abstract: Rather than comparing an old file with a new file to generate a set of patching instructions, and then compressing the patching instructions to generate a compact patch file for transmission to a user, a patch file is generated in a single operation. A compressor is pre-initialized in accordance with the old version of the file (e.g. in an LZ77 compressor, the history window is pre-loaded with the file). The pre-initialized compressor then compresses the old file, producing a patch file from which the new file can be generated. At the user's computer, a parallel process is performed, with the user's copy of the old file being used to pre-initialize a decompressor to which the patch file is then input. The output of the decompressor is the new file. The patch files generated and used in these processes are of significantly reduced size when compared to the prior art.

Abstract: A method of communicating a data word via a bus includes driving the data word onto the bus in whichever one of a true polarity form and a complement polarity form that requires fewer bus lines to change state relative to a present state of each bus line, and providing an indicator signal to the bus to indicate which polarity form of the data word is driven onto the bus. The data word and the indicator signal may be received from the bus, and the polarity form of the data word is conditionally inverted in response to the indicator signal. A noise reduction system includes, for one embodiment, a sending circuit which compares each bit of a data word to be next communicated onto the bus against a corresponding bit of the present data word on the bus. If more than half the bits differ, then the next data word is inverted to form a complement next data word.

Abstract: A unique data label is affixed to each tracked asset and a unique data label for each location in the enterprise, both real and virtual locations. Location history data of the asset is related to other asset data in a relational data base. Assets typically include system components down to the least repairable/replaceable unit (LRU). The data label, in the preferred embodiment of the invention, is a code label using a code that ensures each label is unique to the asset or location to which it is attached. Here the word location is an inclusive term. It includes the geographical location and the identity of the building in which the asset is housed. Location also includes the identity of the system of which a component is a part and, if relevant, location within the system. It includes also any real or virtual location of interest for subsequent analysis and is ultimately defined by the nature of the system being tracked.

Abstract: The present invention provides for an apparatus for transferring information in a network computing system environment. The apparatus comprises of a main storage and an information transfer interface mechanism in processing communication with the main storage. The interface mechanism is capable of coupling to a plurality of input/output devices. The apparatus also comprises of means for transferring a packet of data between the interface mechanism and the main storage and means for concurrently transferring and processing a plurality of other packets of data between the interface mechanism and said main storage.

Abstract: A system for allocating shared memory resources among a plurality of queues and discarding incoming data as necessary. The shared memory resources are monitored to determine a number of available memory buffers in the shared memory. A threshold value is generated for each queue indicating a maximum amount of data to be stored in the associated queue. Threshold values are updated in response to changes in the number of available memory buffers.

Abstract: An apparatus, functioning as a user-input device (UID) to a computer by using a communication link, receives/transmits additional I/O signals via the same link. The I/O signals may be analog or digital. One implementation of the apparatus, made wireless and supported by speech processing software, allows its user to interact with the computer remotely. The inventive apparatus comprises means for converting the I/O signals into/from the digital I/O streams in such a manner as to be transferable to/from the computer along with the UI information via the same communication link. The apparatus, while functioning as a UID, may handle the I/O signals coming from/to an external I/O device, such as a fax/modem device or even another conventional UID. The apparatus, while performing as a UID, may include the complete functionality of an external I/O device handling the I/O signals.

Abstract: A method and apparatus for transferring data in a computer system between a first memory region and second memory region in a single Direct Memory Access (DMA) operation. The first memory region, the second memory region, or both the first and second memory regions can include sub-regions of sequentially-addressable memory locations that are separated, within their respective regions, by a stride. The method and apparatus are particularly well adapted for use in computer graphics systems that include one or more regions of memory, such as frame buffers, that are organized in a rectangular manner as a plurality of contiguous but not sequentially-addressable memory locations within the memory of the graphics system.

Abstract: Rather than comparing an old file with a new file to generate a set of patching instructions, and then compressing the patching instructions to generate a compact patch file for transmission to a user, a patch file is generated in a single operation. A compressor is pre-initialized in accordance with the old version of the file (e.g. in an LZ77 compressor, the history window is pre-loaded with the file). The pre-initialized compressor then compresses the old file, producing a patch file from which the new file can be generated. At the user's computer, a parallel process is performed, with the user's copy of the old file being used to pre-initialize a decompressor to which the patch file is then input. The output of the decompressor is the new file. The patch files generated and used in these processes are of significantly reduced size when compared to the prior art.

Abstract: Data transfer scheme wherein data transfer rates can be effectively doubled with no increase in the clock speed of the interface. This is accomplished by allowing more than one data transfer to occur on a single clock cycle. This transfer scheme increases the transfer rate of the interface by multiplexing two data groups on the same interface. These data groups are transmitted from a source phase latch at approximately the same time as two strobe signals which have low skew with respect to the data. The master and slave strobe signals are logically combined to create an even latch enable signal and an odd latch enable signal that are used to latch and de-multiplex the multiplexed data groups at a receiving end of a pair of flow-though source synchronous latches.

Abstract: A PC-based home automation system uses a low data-rate transport layer and COM-based software components for control of devices in a home automation network. The home automation system is merged with a messaging-based HAVi-network that uses IEEE 1394 as a high data-rate transport layer. The HAVi-network controls audio/video equipment in a home entertainment system. The home automation services and devices are registered as a HAVi-compliant elements with the HAVi network's FAV or IAV device. The home automation resources (devices and services) have both COM OLE Automation Interfaces and HAVI-compliant interfaces to permit control of the home automation system from the HAVi-network.

Abstract: A method and apparatus provide a mechanism for a personal computer to allow the insertion and removal of devices to and from device ports without re-starting the operating system of the computer. Device drivers are pre-loaded during the start-up process of the computer system for devices that may be inserted in the system later. Upon detection of device insertion, a high priority thread process determines the type of device inserted and determines which pre-loaded device driver can operate the newly inserted device. The selected device driver is linked to the file system and is activated by signaling to the device driver or to the operating system of the existence of the newly inserted device. The operating system can then operate the inserted device. Upon device removal, device drivers for the removed device can be deactivated. The system also allows a docking station to have devices added or removed from device ports after the docking process has been completed.

Abstract: The present invention provides for a computer program product for use with a computer system having a main storage device in processing communication with an information transfer interface mechanism capable of coupling to a plurality of input/output devices. The computer program device comprises of a data storage element included in the main storage device having a computer usable medium with computer readable program means for receiving and retrieving data and computer readable code means for concurrently receiving multiple packets of data from said interface mechanism. It also includes computer readable code means for concurrently storing multiple packets of data concurrently in said data storage element as well as computer readable code means for storage and retrieval of multiple packets of data concurrently between said interface mechanism and said data storage element.

Abstract: A real time “plug and play” installation mechanism which, instead of signaling the operating system to activate a pre-existing installation file previously shipped with the operating system file structure, energizes the operating system to retrieve the installation from a remote source. Examples of locations from which the installation resources may be retrieved include (1) an internet universal resource location (URL), (2) a dial-up bulletin board service (BBS), (3) a local area network (LAN) or wide area network (WAN) in which any required access protocols are supplied with the new device being installed, or (4) non-volatile storage (e.g. firmware) physically located on the new device being installed. The device manufacturer gives the operating system manufacturer a special installation file at the time that the operating system manufacturer distributes a new release. The special file appears to the operating system to be a conventional installation file.

Abstract: A network interface device includes a random access transmit buffer and a random access receive buffer for transmission and reception of transmission and receive data frames between a host computer bus and a packet switched network. The network interface device includes a memory management unit having read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The memory management unit also includes a synchronization circuit that controls arbitration for accessing the random access memories between the read and write controllers. The synchronization circuit asynchronously monitors the amount of data stored in the random access transmit and receive buffer by asynchronously comparing write pointer and read pointer values stored in gray code counters, where each counter is configured for changing a single bit of a counter value in response to an increment signal.

Abstract: A smart card comprises a microcontroller, a memory unit, a storage unit, and a communications unit. The smart card may be connected to a terminal, which is in turn may be connected to a host computer and/or a network. The smart card is configured to initiate communications with the terminal, which enables the smart card to control the terminal, host computer, or network and to access the resources connected to the terminal, host computer, or network. A communications protocol defines the commands that the smart card can send and allows the smart card to communicate using asynchronous or logical asynchronous communication.

Abstract: A network interface device includes a random access memory used as a transmit and receive buffer for transmission and reception of data frames between a host computer bus and a packet switched network. The network interface device includes read and write controllers for each of the transmit and receive buffers, where each write controller operates in a clock domain separate from the corresponding read controller. The read and write controllers output status information corresponding to the reading or writing of a stored data frame in the receive buffer. The memory management unit includes a synchronization circuit, which arbitrates updates to the holding registers by the read and write controllers based on the asynchronously determined presence of at least one stored data frame.

Abstract: A system includes a computer and digital camera connected to each other; automatic image transfer or remote control can be achieved readily, and a power supply route is simple. A card connector for an I/O card and a back connector thereof are linked by a power supply line. When the I/O card is connected to a digital camera, power supplied over an interface cable joined with the back connector is supplied to the digital camera. Moreover, when the I/O card is connected to the digital camera, a start-up instruction signal is sent from the I/O card to the digital camera. A CPU in the digital camera executes start-up processing.