Patents Examined by Katharina Schuster
  • Patent number: 6145030
    Abstract: An apparatus includes an input/output (I/O) address verification unit that determines whether an I/O address received from a processor is protected. An interrupt generator is coupled to the I/O address verification unit. The interrupt generator generates an interrupt if the I/O address is protected. An interrupt recorder is coupled to the address verification unit. The interrupt recorder records a cause of the interrupt.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: November 7, 2000
    Assignee: Intel Corporation
    Inventor: Andrew Martwick
  • Patent number: 6141701
    Abstract: A system for, and method of, off-loading network transactions from a mainframe to an intelligent input/output device, including off-loading message queuing facilities. A storage controller has a processor and a memory, in which the controller receives I/O commands having corresponding addresses. In the controller memory, a communication stack is provided for receiving and transmitting information on a network. In addition, a message queue facilities (MQF) is provided that cooperates with the communication stack and that is responsive to a message queue verb. The MQF causes the communication stack to provide information to a queue in the MQF or causes a queue in the MQF to provide information to the communication stack. Moreover, interface logic is provided in the controller memory and is responsive to the I/O commands, to determine whether an I/O command is within a first set of predetermined I/O commands.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: October 31, 2000
    Inventor: Mark M. Whitney
  • Patent number: 6119174
    Abstract: The value of a p-quantile of a workload distribution is computed to determine whether a data storage system satisfies a quality-of-service guarantee desired by a client. The quality-of-service guarantee may be a predetermined percentage of a workload being serviced by a device within a predetermined response time. A p-quantile value is set to be equal of the predetermined percentage of the quality-of-service guarantee, and a bound is set to be equal to the predetermined response time. A distribution for the workload arriving at the device during an interval of time equal to the bound is then estimated. It is then determined whether a p-quantile of the workload distribution is less than the bound. In cases where the p-quantile of the workload distribution is computed directly, then the p-quantile of the workload distribution is directly compared to the bound.
    Type: Grant
    Filed: October 13, 1998
    Date of Patent: September 12, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Elizabeth L. Borowsky, Richard A. Golding, Arif A. Merchant, Mirjana Spasojevic, John Wilkes
  • Patent number: 6105154
    Abstract: A test system resident in a highly integrated chip having a multi-bus architecture and data transfer protocols among a plurality of modules comprising a plurality of buses, each of the buses having multiple data lines for transferring data based on the data transfer protocols, a multiplexer coupled to the plurality of buses for multiplexing the data onto parallel lines and a CRC signature compactor coupled to the parallel lines for receiving the data. The CRC signature compactor compresses the data and (1) provides a fault-free signature representative of the data in a known fault-free chip, and (2) provides another signature representative of the data in a chip under test, wherein the two signatures are compared to determine whether a fault exists in the chip under test.
    Type: Grant
    Filed: May 29, 1998
    Date of Patent: August 15, 2000
    Assignee: Lucent Technologies, Inc.
    Inventors: Andrew A. Wang, Michael J. Weber
  • Patent number: 6105077
    Abstract: A transmitting system including a controller for supervising an address polling system; and a plurality of transmitting modules; connected in cascade to a pair of transmitting paths extending from the controller, for executing polling transmissions from the controller by using a logical address set in each transmitting module; wherein the controller sends a command message for setting the logical address and each transmitting module includes: a switching element circuit for opening and closing between input and output terminals connected to the transmitting paths; and a signal processing circuit for setting the logical address to an address assigned by the command message when a polling address of the command message is identical to the logical address, and for providing a signal to the switching element circuit according to the logical address.
    Type: Grant
    Filed: January 21, 1998
    Date of Patent: August 15, 2000
    Assignee: Nittan Company, Limited
    Inventor: Tetsuo Kimura
  • Patent number: 6098139
    Abstract: A clock crossing FIFO capable of functioning regardless of relative clock frequencies on the write and read sides. Toggle signals are utilized to cross the clock boundaries. The number of write counts which have been accrued but not acknowledged by the read side are tracked, and this number is stored as of the issuance of a write toggle. Upon toggle receipt on the read side, this number is latched as a measure of the number of data units which can be read from the FIFO. At the same time, the toggle is returned to the write side for decrementing the number of write counts outstanding by the number conveyed to the read side. Similar circuitry is employed for conveying to the write side circuitry the number of data units which have been read by the read side circuitry. The presently disclosed FIFO and associated circuitry operates independent of relative clock speeds, and the particular size of the FIFO is scalable.
    Type: Grant
    Filed: May 27, 1998
    Date of Patent: August 1, 2000
    Assignee: 3Com Corporation
    Inventors: Paul J. Giacobbe, Robert P. Ryan
  • Patent number: 6092130
    Abstract: The present invention has an object to provide a data padding apparatus capable of appropriate padding processing to input data and input insignificance information which are not synchronized. Receiving input data and input significance information which are not synchronized as inputs, the data padding apparatus performs synchronization by data storage means and significance information storage means included in a storage and padding means, generates original data and synchronized significance information with synchronism between them and outputs them to a padding information holding means where padding information consisting of padding data and padding address information is generated based on the data and information input.
    Type: Grant
    Filed: February 26, 1998
    Date of Patent: July 18, 2000
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Kazuyoshi Horiike
  • Patent number: 6092135
    Abstract: Disclosed is a computer system for reducing booting time. The computer system includes a sensor unit detecting whether a main body of the computer system is assembled or disassembled. The sensor unit outputs low and high signals when a bottom case of the main body is assembled and disassembled, respectively, from a top case of the main body. The computer system also includes a memory, a state of which is changed according to the signals output from the sensor unit, and which stores information of assembly and disassembly states of the main body, and a controller for selectively executing a specific program according to the state of the memory when power is supplied to the computer system.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: July 18, 2000
    Assignee: SamSung Electronics Co., Ltd.
    Inventor: Eun-Sook Kwon
  • Patent number: 6081855
    Abstract: A media player includes an input manager and an input driver. The input manager operates between a device driver and a player application program. The input manager provides a uniform interface for input drivers and, upon receiving a command from an input driver passes the command along to an application program. The input manager ranks input devices according to a user's preferences and, should the input manager receive commands from more than one device driver at one time, the input manager passes along the commands in accordance with the user's input device preferences. Each input device driver provides the input manager with an indication of the driver's capabilities so that the input manager passes the appropriate information, such as location information in the case of a location sensitive input device's driver, to the driver. Each input device driver also performs the translation of input signals into a format that is acceptable by the input manager.
    Type: Grant
    Filed: April 15, 1998
    Date of Patent: June 27, 2000
    Assignee: Oak Technology, Inc.
    Inventor: Linden A. deCarmo
  • Patent number: 6078982
    Abstract: A system for allowing consistent execution of a workflow process in a computer-enabled workflow management system is described. The system includes a workflow process database accessible by the workflow process. The workflow process includes at least one sequence of workflow actions, having at least one set of parallel workflow actions and being configured as a plurality of nodes interconnected by arcs. Each node defines at least one of the workflow actions and reading and writing data items when executing the workflow actions. A first module is provided to lock all data items in the workflow process database that are specified for access by the workflow process from being accessed by other workflow processes during execution of the workflow process before the execution of the workflow process is commenced.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: June 20, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Weimin Du, Ming-Chien Shan, Ahmed Elmagarmid
  • Patent number: 6055592
    Abstract: A mouse system (100) for authenticating a user and providing access to a computer (212) includes a pointing device and card reader (106) which share a computer interface port (222) of the computer (212). User information is read off the card (104), converted to pointing device codes, and provided to the computer (212). The computer reconverts the pointing device codes to user information to deny or grant access. The card reader (106) is capable of reading commercially available smart cards, credit cards, and other media having user information electronically stored on the card (104).
    Type: Grant
    Filed: February 9, 1998
    Date of Patent: April 25, 2000
    Assignee: Motorola, Inc.
    Inventor: Robert Neal Smith
  • Patent number: 6041369
    Abstract: An improved apparatus and method for monitoring and controlling when a data phase in a burst transmission of data is about to end. The apparatus described interleaves dual adder circuits such that each dual adder circuit has more time to process incoming data. Distribution of the processing allows slower, lower cost components to be used in high speed applications. The described apparatus and method are particularly useful in peripheral component interconnect applications.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: March 21, 2000
    Assignee: Sun Microsystems, Inc.
    Inventor: John Watkins