Patents Examined by Kaushikkumar Patel
  • Patent number: 10168960
    Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, Jr., Harris M. Morgenstern, James H. Mulder, Elpida Tzortzatos, Dieter Wellerdiek
  • Patent number: 10120612
    Abstract: An apparatus, method, system, and program product are disclosed for tape copying. One method includes mounting a first source tape of multiple source tapes on a source tape drive. The method includes mounting a destination tape on a destination tape drive. The method also includes copying a first index of an index partition of the first source tape to a first copied index of an index partition of the destination tape. The method includes storing first position information corresponding to the first copied index on the destination tape. The method also includes copying first data of a data partition of the first source tape to a first copied data of a data partition of the destination tape. The method includes storing second position information corresponding to the first copied data on the destination tape.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Hiroshi Itagaki, Sosuke Matsui, Shinsuke Mitsuma, Tsuyoshi Miyamura, Noriko Yamamoto
  • Patent number: 10095589
    Abstract: A method and system is provided for optimization of restoration and loading of an operating system of a computer. An exemplary method includes initiating a loading of the operating system of the computer and intercepting a read request of data of a data volume from the operating system. Furthermore, the method includes determining whether the data has previously been restored during the loading of the operating system, and, if the data has previously been restored, performing the read request and returning to the loading of the operating system of the computer. Alternatively, if the data has not previously been restored, determining whether the data is stored in cache of the computer. If the data is not be stored in the cache, the method includes reading the data from a data archive and storing the data read from the data archive to the cache.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 9, 2018
    Assignee: ACRONIS INTERNATIONAL GMBH
    Inventors: Maxim V. Lyadvinsky, Andrey Redko, Ivan Kukhta, Anatoly Stupak, Serguei Beloussov, Stanislav M. Protassov, Mark Shmulevich
  • Patent number: 10095439
    Abstract: According to one embodiment, a tiered storage system includes first and second storage devices having access speeds different from each other, and a storage controller. The storage controller manages first and second access frequency statistical values. The first access frequency statistical value corresponds to a state in which data of a respective one of logical chunks is located on the first storage device, and the second access frequency statistical value corresponds to a state in which data of the respective one is located on the second storage device. The storage controller determines whether it is necessary to change the location state of the data of the respective one, based on the first and second access frequency statistical values of the respective logical chunks.
    Type: Grant
    Filed: August 4, 2016
    Date of Patent: October 9, 2018
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Solutions Corporation
    Inventor: Yasuhiro Ono
  • Patent number: 10089230
    Abstract: Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 2, 2018
    Assignee: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M Cimini, Abhishek R. Appu
  • Patent number: 10083127
    Abstract: Systems and methods for generating a self-ordering buffer are described. An example method includes generating a plurality of nodes forming a linked list, each node in the linked list having a directional pointer referencing a subsequent element in the linked list and a data pointer referencing a corresponding memory block from a plurality of memory blocks; generating a head pointer, the head pointer referencing a beginning node in the linked list; generating a tail pointer, the tail pointer referencing an end node in the linked list; generating a next pointer, the next pointer referencing a next node of the linked list; generating a free pointer, the free pointer referencing a free node of the linked list; and wherein the plurality of nodes forming the linked list, the corresponding memory blocks, the head pointer, the tail pointer, the next pointer, and the free pointer form a buffer.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 25, 2018
    Assignee: HGST Netherlands B.V.
    Inventor: Mohammed Ghiath Khatib
  • Patent number: 10067714
    Abstract: A data storage device includes a first controller; a scale-out storage device; and an interface connected between the first controller and the scale-out storage device, wherein the first controller is configured to transmit, to the scale-out storage device through the interface, a first command including a command type and command information having a parameter with respect to the command type, wherein the scale-out storage device is configured to perform an operation corresponding to the first command, and wherein the scale-out storage device includes, a scale-out controller connected to the interface, a volatile memory connected to the scale-out controller, and a non-volatile memory connected to the scale-out controller.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: September 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Nam Wook Kang, Yang Sup Lee, Da Woon Jung
  • Patent number: 10061513
    Abstract: A packet processing system having a control path memory of a control path subsystem and a datapath memory of a datapath subsystem. The datapath subsystem stores packet data of incoming packets and the control path subsystem performs matches of a subset of packet data, or a hash of the packet data, against the contents of a the control path memory in order to process the packets. The packet processing system enabling a portion of the datapath memory to be used by the control subsystem if needed or a portion of the control path memory to be used by the datapath subsystem if needed.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: August 28, 2018
    Assignee: Cavium, Inc.
    Inventors: Enrique Musoll, Weihuang Wang
  • Patent number: 10055145
    Abstract: The disclosure relates to data protection management for geographically distributed storage systems. Specifically, the present disclosure provides a mechanism for load balancing by combining the techniques of XOR Star and XOR Chain to control the protection of data internally. The load balancing is done by each zone without the need for an external load balancer. In addition, the load balancing mechanism provides the ability for native (e.g. without additional configuration) support of disaster recovery.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: August 21, 2018
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Mikhail Danilov, Alexander Rakulenko, Gregory Skripko, Kirill Zakharov, Andrey Kurilov
  • Patent number: 10042580
    Abstract: A lower level cache receives, from a processor core, a plurality of copy-type requests and a plurality of paste-type requests that together indicate a memory move to be performed, as well as a barrier request that requests ordering of memory access requests prior to and after the barrier request. The barrier request precedes a copy-type request and a paste-type request of the memory move in program order. Prior to completion of processing of the barrier request, the lower level cache allocates first and second state machines to service the copy-type and paste-type requests. The first state machine speculatively reads a data granule identified by a source real address of the copy-type request into a non-architected buffer. After processing of the barrier request is complete, the second state machine writes the data granule from the non-architected buffer to a storage location identified by a destination real address of the paste-type request.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Guy L. Guthrie, Derek E. Williams
  • Patent number: 10037281
    Abstract: An invention is provided for handling target disk access requests during disk defragmentation in a solid state drive caching environment. The invention includes detecting a request to access a target storage device. In response, data associated with the request is written to the target storage device without writing the data to the caching device, with the proviso that the request is a write request. In addition, the invention includes reading data associated with the request and marking the data associated with the request stored in the caching device for discard, with the proviso that the request is a read request and the data associated with the request is stored on the caching device. Data marked for discard is discarded from the caching device when time permits, for example, upon completion of disk defragmentation.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: July 31, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Pradeep Bisht, Jiurong Cheng
  • Patent number: 10031677
    Abstract: Disclosed herein are techniques for implementing high-throughput low-latency hybrid memory modules with improved data backup and restore throughput, enhanced non-volatile memory controller (NVC) resource access, and enhanced mode register setting programmability. Embodiments comprise a command replicator to generate sequences of one or more DRAM read and/or write and/or other commands to be executed in response to certain local commands from a non-volatile memory controller (NVC) during data backup and data restore operations. Other embodiments comprise an access engine to enable an NVC in a host control mode to trigger entry into a special mode and issue commands to access a protected register space. Some embodiments comprise a mode register controller to capture and store the data comprising mode register setting commands issued during a host control mode, such that an NVC can program the DRAM mode registers in an NVC control mode.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: July 24, 2018
    Assignee: Rambus Inc.
    Inventors: Aws Shallal, Michael Miller, Stephen Horn
  • Patent number: 10031687
    Abstract: A computer-implemented method includes identifying a prioritized storage tier; identifying one or more newly allocated data artifacts each associated with a newly allocated data access density value; and identifying one or more optimized data artifacts each associated with an optimized data access density value. The computer-implemented method further includes determining a threshold access density value based on each newly allocated data access density value and determining a prioritized tier organization scheme associated with the prioritized storage tier based on the threshold access density value. A corresponding computer program product and computer system are also disclosed.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: July 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Shan Fan, Yang Liu
  • Patent number: 10031862
    Abstract: A memory protection unit including hardware registers for entering address tables, a configuration memory for storing the address tables, a preconfigured hardware logic for managing the configuration memory, a data connection between the configuration memory and the hardware logic for loading the hardware registers, a first interface for controlling the loading by a computing core, and a second interface for writing to the configuration memory by the computing core.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: July 24, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventors: Gunnar Piel, Nico Bannow, Simon Hufnagel, Jens Gladigau, Rakshith Amarnath
  • Patent number: 10019179
    Abstract: A memory device includes a non-volatile semiconductor memory including a plurality of first areas, each corresponding to an erasing unit, each of the first areas including a plurality of second areas, each corresponding to a writing unit and a controller configured to erase data stored in a first area of the non-volatile semiconductor memory, track amount of time elapsed since the erasure of data from the first area, and write data into one or more unwritten second areas of the first area in accordance with the elapsed time, independent of a command to write data into the unwritten second areas.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: July 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Akihide Jinzenji
  • Patent number: 10007437
    Abstract: A management apparatus includes a memory and a processor coupled to the memory. The processor is configured to: sequentially read data from a movement-target storage area of a storage device included in a first storage apparatus when the data stored in the movement-target storage area is to be moved from the first storage apparatus to a second storage apparatus which is accessible at a higher speed than the first storage, the first storage apparatus including the storage device and a cache memory configured to cache the data stored in the storage device using a write-back scheme; read changed data among the pieces of data in the movement-target storage area from the cache memory; merge data read from the movement-target storage area and the changed data read from the cache memory; and write merged data to the second storage apparatus.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: June 26, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Kazuichi Oe
  • Patent number: 10002020
    Abstract: A data processing apparatus and method of data processing are provided, which relate to the operation of a processor which maintains a call stack in dependence on the data processing instructions executed. The processor is configured to operate in a transactional execution mode when the data processing instructions seek access to a stored data item which is shared with a further processor. When the processor enters its transactional execution mode it stores a copy of the current stack depth indication and thereafter, when operating in its transactional execution mode, further modifications to the call stack are compared to the copy of the stack depth indication stored. If the relative stacking position of the required modification is in a positive stack growth direction with respect to the copy stored, the modification to the call stack is labelled as non-speculative.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: June 19, 2018
    Assignee: ARM Limited
    Inventors: Matthew James Horsnell, Stephan Diestelhorst
  • Patent number: 9996298
    Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to receipt of the paste-type request, the lower level cache issues a command to write the data granule from the non-architected buffer to the memory-mapped device. In response to receipt from the memory-mapped device of a busy response, the processor core abandons the memory move instruction sequence and performs alternative processing.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams
  • Patent number: 9990152
    Abstract: A data writing method is provided. The method includes writing a first write data into a first physical sub-unit in a storage device according to a first write command; recording a first meta data corresponding to the first write data into the storage device; writing a second write data into a second physical sub-unit in the storage device; recording a second meta data corresponding to the second write data into the storage device. A second write identification code of the second meta data is set to be different from a first write identification code of the first meta data if the second physical unit is closely adjacent to the first physical unit and the second write data is written according to the second write command; and whether the second write data is valid or invalid is determined according to the second meta data if a special event occurs.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: June 5, 2018
    Assignee: EpoStar Electronics Corp.
    Inventors: Hung-Chih Hsieh, Yu-Hua Hsiao, Shih-Tien Liao
  • Patent number: 9990282
    Abstract: An address range expander associated with a processor and a physical memory device determines that address transformation has been enabled with respect to an address indicated on the processor's address bus. The expander generates, using one or more address expansion parameter registers, a transformed address corresponding to the untransformed address within an address range of the physical memory device, and transmits the transformed address to a controller of the physical memory device.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 5, 2018
    Assignee: Oracle International Corporation
    Inventors: Joseph Wright, Erik Michael Schlanger, Eric DeVolder