Abstract: A synchronization capability to synchronize updates to page tables by forcing updates in cached entries to be made visible in memory (i.e., in in-memory page table entries). A synchronization instruction is used that ensures after the instruction has completed that updates to the cached entries that occurred prior to the synchronization instruction are made visible in memory. Synchronization may be used to facilitate memory management operations, such as bulk operations used to change a large section of memory to read-only, operations to manage a free list of memory pages, and/or operations associated with terminating processes.

Abstract: A storage control device controlling a storage system including a first storage device and a second storage device, the first storage device and the second storage device include a plurality of regions for storing data, respectively, a data transmission between the first storage device and the second storage device is executed by the region, the storage control device includes a memory, and a processor coupled to the memory and configured to determine a first region of the first storage device as a first transmitting target region, the first region having a first size, transmit, from the first storage device to the second storage device, second data having a second size smaller than the first size, and based on a response performance of the storage system during the transmitting of the second data, transmit first data stored in the first region from the first storage device to the second storage device.

Abstract: Embodiments of the claimed subject matter provide systems and methods for protecting data in dynamically allocated regions of memory. The method can include receiving the read request where the read request comprises a virtual address associated with a memory and determining a physical address associated with the virtual address. The further includes determining whether the physical address associated with the virtual address is read protected and determining whether the read request is from a component allowed to access read protected memory. The read protected memory was dynamically allocated on a per page basis. The method further includes in response to determining that the read request is to a read protected physical address and determining that the component is allowed to access read protected memory, sending the data from the physical address in the memory.

Abstract: A virtual disk conversion system determines location ranges for data on a storage device that are found in files representing a virtual disk in a source format. An intermediate virtual disk data structure containing the location ranges for the data is generated, and the intermediate virtual disk data structure is used to associate data at the location ranges with a new file on the storage device that represents a virtual disk in a destination format.

Abstract: A memory system may include: a data storage unit comprising a first memory device through which data are inputted/outputted through a first channel and a second memory device through which data are inputted/outputted through a second channel, wherein each of the first and second memory devices comprises a plurality of blocks each having multi-level cells (MLCs); and a controller suitable for selecting a first target block among the plurality of blocks of a channel which includes a first victim block and selecting a second target block among the plurality of blocks of a channel of which does not include the first victim block, and separating data of the MLCs included in the first victim block on a level basis and copying the separated data into the first and second target blocks, respectively, during a garbage collection operation.

Abstract: Provided method includes storing a first cache snap shot including cache profiling information regarding a cache when a first process being executed by a cycle accurate simulator is terminated; storing a second cache snap shot including the cache profiling information on the cache when a second process is executed in the cycle accurate simulator; comparing the second cache snap shot of the second process and the first cache snap shot of the first process to readjust any one value of a cache hit value and a cache miss value which are present in the second cache snap shot of the second process; and correcting the cache profiling information which is stored in the first cache snap shot of the first process by reflecting the readjusted any one value of the cache hit value and the cache miss value present in the second cache snap shot of the second process.

Abstract: Various embodiments mitigate busy time in a hierarchical store-through memory cache structure including a cache directory associated with a memory cache. The cache directory is divided into a plurality of portions each associated with a portion of memory cache. A determination is made that a first subpipe of a shared cache pipeline comprises a non-store request. The shared pipeline is communicatively coupled to the plurality of portions of the cache directory. A store command is prevented from being placed in a second subpipe of the shared cache pipeline based on determining that a first subpipe of the shared cache pipeline comprises a non-store request. Simultaneous cache lookup operations are supported between the plurality of portions of the cache directory and cache write operations. Two or more store commands simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.

Abstract: According to embodiments, a controller comprises a write control unit that performs writing in a nonvolatile semiconductor memory, and an area management unit that causes the write control unit to perform write processing until a spare area not storing valid data is not present in the nonvolatile semiconductor memory, and transmits an error to a host when the spare area is not present.

Abstract: A mixed cache is indexed to main memory and page coloring is applied to map main memory to virtual memory. A nursery array and a mature array are indexed to virtual memory. An access to a virtual page from the mixed cache is recorded by determining an index and a tag of an array address based on a virtual address, following the index to corresponding rows in the nursery and the mature arrays, and determining if the tag in the array address matches any tag in the rows. When there is a match to a tag in the rows, an access count in a virtual page entry corresponding to the matched tags is incremented. When there is no match, a virtual page entry in the row in the nursery array is written with the tag in the array address and an access count in the entry is incremented.

Abstract: Methods, systems and/or devices are used for limiting write command execution in a storage device comprising a set of non-volatile memory devices. In one aspect, the method includes (1) accessing in a holding queue host-specified write commands specified by a host system, each of the host-specified write commands specifying a number of pages to be written to the set of non-volatile memory devices; (2) in accordance with a determination that throttling is enabled: (3) determining a limit number of pages for a current throttle period in accordance with a throttle rate, the throttle rate being a maximum write rate for executing host-specified write commands; and (4) during the current throttle period, moving from the holding queue to a pending queue, for execution by the set of non-volatile memory devices, host-specified write commands whose total specified number of pages does not exceed the limit number of pages.

Abstract: A data storage device including a flash memory and a controller. The flash memory includes a plurality of dies having a plurality of columns, wherein each of the columns is constituted by a plurality of sectors. The controller performs a read operation or a write operation from a first column to an Nth column in response to a read command or a write command, and skips at least two columns within the range of the first column to the Nth column according to a first bad column data set, wherein the first bad column data set has a starting address and the number of columns.

Abstract: An arbitration system and method is disclosed. The apparatus includes a first and a second memory devices, and a resistor coupled in common to the first and second memory devices, the first memory device includes a first calibration circuit configured to perform a first calibration operation responsive, at least in part, to an external calibration command, the first calibration operation being performed based on the resistor, and the second memory device includes a second calibration circuit configured to perform a second calibration operation responsive, at least in part, to the external calibration command, the second calibration operation being performed based on the resistor after the first calibration operation has finished.

Abstract: Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to operate on a first data element in the cache memory, perform a lookup operation for the first data element in the volatile memory and in response to a failed lookup operation, to generate a cache scrub hint forward the cache scrub hint to a cache scrub engine and identify one or more cache lines to scrub based at least in part on the cache scrub hint. Other examples are also disclosed and claimed.

Abstract: A system for write-once memory (WOM) code emulation of EEPROM-type devices includes, for example, a host processor for sending data words for storing in a WOM (Write-Only Memory) device. A host interface receives the data words for encoding by a WOM controller. An emulator programs the WOM-encoded data and an address identifier as an entry of the WOM device. The emulator overwrites previously programmed WOM-encoded data by searching entries of a current active page of a WOM device to locate a programmed WOM entry that includes the searched-for address identifier and the previously written WOM-encoded data word. When the previously written WOM-encoded word cannot be correctly overwritten, the contents of the second WOM-encoded word are stored in a new entry. When the current active page is substantially full, the new entry is stored a new page and the current active page is block-erased.

Abstract: A non-volatile computer memory has instructions executed by a processor to create an array of pages, where each page is configured with individual chunks of memory to receive serialized data. The array of pages is positioned as an on-heap slab of at least 200 GB in a garbage collector managed area of a virtual machine memory.

Abstract: A storage device associated with a storage array may be identified. Information specifying an organization of data included in a data structure may be retrieved from the storage device. The data may be associated with characteristics of a plurality of data blocks of the storage device. A read operation or a write operation may be performed for the storage device based on the information specifying the organization of the data included in the data structure that is associated with the characteristics of the plurality of data blocks of the storage device.

Abstract: Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including allocating, by a storage manager, a virtual memory page to a memory buffer that is used by an application being executed by a multiprocessor system, the virtual memory page being allocated from an address space of the application. The method also includes recording, by a memory management unit, a mapping between the virtual memory page and a physical location in a memory. The method also includes in response to a request, from the application, to deallocate the memory buffer, delaying invalidation of the mapping between the virtual memory page and the physical location in a memory, based on a count of free frames in the address space of the application.

Abstract: A method of caching data in the memory of electronic processor units including compiling, in a first processor configured to perform data-parallel computation, a set of asymmetric coherent caching rules. The set of rules configure the first processor to be: inoperable to cache, in a second level memory cache of the first electronic processor unit, data whose home location is in a final memory store of a second electronic processor unit; operable to cache, in the second level memory cache of the first electronic processor unit, the data whose home location is in a final memory store of the first electronic processor unit; and operable to cache, in a first level memory cache of the first electronic processor unit, the data, regardless of a home location of the data.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: Output is produced from a memory block. A key memory is accessed to produce memory output based on a value of a first index. The memory output includes a stored compressed key and a stored index. A compressed key is produced based on the uncompressed key. The produced compressed key is compared with the stored compressed key. The stored index is output when the stored compressed key matches the produced compressed key.