Abstract: A method for forming uniformly sized features, such as polysilicon lines or gates, or such as conductive lines, on a semi conductor wafer having a planar upper surface is described which minimizes variations in the critical dimensions of the features. The technique allows a substantially uniform overlying layer, such as photoresist, to be formed above the layer intended to contain the features. The method can be applied to forming isolation trenches around active areas on the semiconductor wafer, overfilling the trenches with an insulating material (e.g., oxide), polishing back the oxide to a planar surface, depositing a planar layer of a conductive material (e.g., poly), and depositing a planar layer of a photoresist. The planar layer of photoresist, being deposited over a planar layer of conductive material has substantially uniform thickness and correspondingly uniform reflectivity.

Abstract: A silicon accelerometer comprising a substrate, one or more pairs of beams, a pedestal, a mass on top of the pedestal and a cavity beneath the pedestal all of which is formed by a single-sided processing method. The pedestal is suspended over the cavity by the beams which provides the only support for the pedestal. The beams are supported by the substrate. The main steps of fabricating this structure comprise diffusion or ion implantation and epitaxial growth to form a buried high donor concentration layer on the surface of the substrate, chemical vapor deposition and photoetching to expose a portion of the edge of the buried layer to the ambiente, anodization to convert the high donor concentration layer into porous silicon and selectively etching to remove the porous silicon.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: The invention concerns a solid alkalimetal silicate having a molar ratio SiO.sub.2 :M.sub.2 O from about 1.5 to about 3, in which M is an alkalimetal substantially consisting of sodium and potassium. The silicate contains from about 1 and up to about 5% by weight of K.sub.2 O based on the dry material and the water content being from about 16 to about 25% by weight based on the total weight.Further, the invention concerns a method of its preparation, its use and a cleaning agent composition containing the silicate above.

Abstract: An improved process for uniformly distributing high levels of water in hydrophilic fumed silica by mixing with dry water.

Abstract: Precipitated silica particulates having a BET specific surface ranging from 20 to 300 m.sup.2 /g, a CTAB specific surface ranging from 10 to 200 m.sup.2 /g, an oil uptake (DBP) ranging from 80 to 400 cm.sup.3 /100 g, a pore volume ranging from 1 to 10 cm.sup.3 /g and a mean pore diameter ranging from 10 to 50 nm, well adapted for such applications as the coating of paper and catalysis, are prepared by (a) simultaneously introducing a silicate and an acid into a dispersion of colloidal silica, thereby providing a silica suspension, (b) next decreasing the pH of such suspension to a value ranging from 3 to 7, and (c) then separating the silica particulates from the final suspension and drying them.

Abstract: Alkali metal silicate solutions are formed into granules in a single stage. The heated solution is sprayed into a heated drum having a multiplicity of arms fixed to a rapid by rotating central shaft. A gas, preferably air, heated to 150.degree. C. to 200.degree. C. is also introduced with the silicate solution and a granulated product is obtained from the other end of the drum.

Abstract: The present invention provides a method for fabricating tungsten local interconnections in high density CMOS circuits, and also provides high density CMOS circuits having local interconnections formed of tungsten. Pursuant to the method, an etch stop layer of chromium is initially deposited on the circuit elements of the CMOS silicon substrate. Next, a conductive layer of tungsten is non-selectively deposited on the chromium layer. A photoresist mask is then lithographically patterned over the tungsten layer. The tungsten layer is then etched down to, and stopping at, the chromium layer, after which the photoresist mask is stripped. The stripping preferably uses a low temperature plasma etch in O.sub.2 at a temperature of less than 100.degree. C. Finally, a directional O.sub.2 reactive ion etch is used to remove the chromium layer selectively to the silicon substrate. Borderless contacts are formed with the aid of the chromium etch stop layer beneath the tungsten local interconnection layer.

Abstract: The invention concerns a solid alkalimetal silicate having a molar ratio SiO.sub.2 :M.sub.2 O from about 1.5 to about 3, in which M is an alkalimetal and substantially consists of sodium and optionally potassium. The silicate contains from about 7 to about 20% by weight of sodium carbonate based on the dry material and has a water content from about 14 to about 22% by weight.Further, the invention concerns a method of preparing the silicate above, use of the same and cleaning agent compositions containing such a silicate.

Abstract: A semiconductor device including a semi-conductor substrate having active regions formed therein, at least one metal wiring pattern formed on the semiconductor substrate, and a final insulating layer formed on the metal wiring pattern. The final insulating layer is made of a borophosphosilicate glass and a plasma CVD silicon nitride film formed on the borophosphosilicate glass film. The borophosphosilicate glass film is formed by a chemical vapor deposition by supplying a gaseous mixture of organic silane, alkoxides of boron and phosphorus and ozone into a reaction vessel under the atmospheric pressure. The thus formed borophosphosilicate glass film has excellent step coverage, so that the plasma CVD film can be formed to have a uniform thickness. Further the plasma CVD film has excellent moisture resistance and water proof properties, and thus the whole insulating layer is particularly suitable as the final passivation layer of the semiconductor device.

Abstract: There is provided a composite oxide represented by the formulaiR.sub.2 O.jAl.sub.2 O.sub.3.kTiO.sub.2.mSiO.sub.2.nH.sub.2 Owherein R denotes an alkali metal, i is 0.3 to 1, k is 0 to 0.9, j+k=1, m is 7 to 70 and n is 0.2 to 0.4, said composite oxide being amorphous, and its cumulative specific pore volume of pores having a pore radius of 10.sup.4 A or less being 2.0 to 3.0 cc/g. This composite oxide can be produced by a process which comprises a first reaction step of adding an acid aqueous solution capable of forming a silicate by reaction with an alkali silicate to 7 to 10% by weight, calculated as silica, of an alkali silicate aqueous solution in the presence of a salt at 10 to 45.degree. C. such that a neutralization ratio becomes 20 to 40%, and a second reaction step of heating the reaction solution obtained in the above reaction at temperature of 90.degree. C.

Abstract: In a semiconductor device, an interconnection of differentially doped diffusion regions formed on a substrate includes an interconnecting layer disposed between the two diffusion regions so that the two regions are coupled to one another. The interconnect region is defined by the existing mask boundaries of N+ dopant and P+ dopant regions such that N+ and P+ dopant is not allowed to enter the interconnect region. Thus, the interconnect region is defined without requiring additional masking and etching steps. Once the interconnect region is defined, then the interconnecting layer is formed by a deposition and sintering process. The interconnecting layer provides a schottky barrier and ohmic contact.

Abstract: A process for the elimination of iron from silica sand, comprising: abrasive-attritioning sand particles by subjecting the sand particles, in a single step and under dry conditions, to centrifugal rotation and simultaneously imparting an agitation with a translative eccentric movement and downstream and upstream movements causing that substantially all the sand particles be abrasive attritioned to each other wearing their surfaces to remove impurities covering said sand particles; and separating said iron impurities from said sand particles by magnetic separation, flotation or other known methods, thus simplifying the conventional processes just to one attrition step and suppressing the chemical treatment with acids or alkalis which was necessary in conventional processes.

Abstract: A method for forming multiple layer metallurgy, spin-on-glass multilayer metallurgy for a one micrometer or less feature size integrated circuit with substantially free field inversion, that is the positive charge between the first via layer and the SOG is described. A semiconductor substrate having a pattern of field effect device source/drain regions therein with a pattern of gate dielectric and gate electrode structures associated therewith and a pattern of field isolation structures at least partially within semiconductor substrate electrically separating certain of these source/drain regions from one another are provided. A passivation layer is formed over the surfaces of said patterns.

Abstract: Low residual stress, stoichiometric or near stoichiometric, silicon nitride and silicon carbide films with thicknesses of one micron or greater are produced by reacting porous silicon with a nitrogen or carbon containing gas, such as ammonia or methane, at an appropriate temperature and pressure. The gas diffuses into the pores and reacts with the silicon skeletal structure. Because the initial structure is porous and the pore spaces provide strain relief during the addition reaction and subsequent volume expansion, the resultant film has relatively low residual stress. Either porous or solid films can be produced. This process provides a means to chemically stabilize porous silicon layers and their morphologies.

Abstract: A method for producing a silicon dioxide film by contacting a substrate such as glass with a treating liquid comprising a hydrosilicofluoric acid solution supersaturated with silicon dioxide to deposit a silicon dioxide film on the surface of the substrate, the method being characterized by providing a device for preventing an Si component from escaping from the treating liquid. According to the method, pollution of working environment and decrease in concentration of solution do not occur during the formation of silicon dioxide film.

Abstract: The hydrogen content of polysilicon can be reduced by heat treatment. The process is preferably conducted on polysilicon particles in bead-like form produced by chemical vapor deposition in a fluidized bed. The heat treatment is preferably conducted at a temperature of 1020.degree.-1200.degree. C. for a time from about 6 hours to about 1 hour sufficient to reduce the hydrogen content, and insufficient to cause agglomeration of the particles being treated. In order to reduce the tendency of particles to agglomerate at the process temperature employed, the particle bed is preferably maintained in motion during the dehydrogenation. The products produced by the process can have a hydrogen content of 30 ppma or less. These improved products can be used to produce monocrystalline silicon for the production of semiconductor devices.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of forming a solid phase diffusion source containing a conductive impurity on a surface of a semiconductor substrate, said impurity serving to enable said semiconductor substrate to exhibit a p-type or n-type conductivity, allowing said solid phase diffusion source to contain a diffusion control substance serving to reduce or oxidize said conductive impurity upon heating so as to change the diffusion coefficient of the conductive impurity contained in the solid phase diffusion source, and thermally diffusing the conductive impurity from the solid phase diffusion source into the semiconductor substrate.

Abstract: A non-silyated, ternary boron nitride film (18, 38) is provided for semiconductor device applications. The non-silyated, ternary boron nitride film is preferably formed by plasma-enhanced chemical vapor deposition using non-silyated compounds of boron, nitrogen, and either oxygen, germanium, germanium oxide, fluorine, or carbon. In one embodiment, boron oxynitride (BNO) is deposited in a plasma-enhanced chemical vapor deposition reactor using ammonia (NH.sub.3), diborane (B.sub.2 H.sub.6), and nitrous oxide (N.sub.2 O). The BNO film has a dielectric constant of about 3.3 and exhibits a negligible removal rate in a commercial polishing apparatus. Because of its low dielectric constant and high hardness, the ternary boron nitride film formed in accordance with the invention can be advantageously used as a polish-stop layer and as a interlevel dielectric layer in a semiconductor device.

Abstract: A method for forming a bipolar emitter using doped SOG which employs diffusion instead of implanting, and which produces a shallow, low-resistance emitter using a variety of dopants besides boron and phosphorus. A layer of doped SOG is spun over a predefined base region. Portions of the SOG layer are defined for removal and removed, leaving the collector and emitter contact areas exposed. The SOG layer is densified and the dopants are driven into the base to form the emitter.