Abstract: A two-hop communications system utilizing two collocated spacecraft (Se and Sw) and two remote intersatellite exchange (RISE) means (Re and Rw) provides for communications between ground stations located in two or more defined subregions. Each satellite includes wide band transponders for relaying ground station transmissions to the RISEs. The RISEs convert first hop frequency division multiplexed (FDM) signals to time division multiplexed (TDM) for the second hop. Signals are coded by frequency, polarization and direction so as to avoid loss of bandwidth due to the two-hop approach.

Abstract: The reliability of a distributed processing system is enhanced through the use of a highly reliable data communication system. Each node of such a system is connected to the other nodes by a local data network, including duplicated data network media, such as coaxial cables. Each node includes a maintenance processor for controlling which of the duplicate network media is active and which is standby. Regular inter-node data packets are transmitted over the active network medium. Control data packets to the maintenance processor are sent from a control node over the standby network medium. The maintenance processor can also totally stop transmission of data from the associated node to both data network media.

Abstract: A microprocessor-based frequency shift keying (FSK) data communications module. The microprocessor selectively modulates and demodulates data directly in terms of a square wave pulse train in which a first frequency is used to convey a binary "1" and a second frequency to convey a binary "0". An input and an output port on the microprocessor are selectively coupled to a transmission line through a transformer, by means of electronic switches. Also included are a bandpass filter for shaping the square waves into sine waves and for filtering noise, and means including a notch filter for generating a carrier detect signal input to the microprocessor, when incoming data is detected on the transmission line. Many of the components in the module are used for both transmitting and receiving data.

Abstract: In a data distributor for distributing an output data signal to an output port in response to an input data signal divisible into a plurality of channel signals arranged in channels, respectively, a position number signal is specific to a position of the data distributor and converted by a converting unit into a specific channel number signal representative of a specific one of the channels. The specific channel number signal is compared by a comparator with each channel number signal received in synchronism with the channel signals, to detect coincidence therebetween. On detection of coincidence, an AND gate allows a part of the input data signal to pass therethrough as the output data signal.

Abstract: A high rate multiplexing system which is capable of operating on multiple channels while ensuring synchronization of the system operation. The system includes a basic timing network for synchronizing the system operation. Automatic phase adjusters are used to re-align data signals with a clock signal whenever data transitions occur while the data is being sampled. Synchronizing circuits are used to insert synchronization data bits into the multiplexed data streams where appropriate. A medium rate multiplexer generates two different data streams, certain clock signals and strobe signals. A higher rate multiplexer is capable of operation in different modes, including but not limited to wideband operation or narrow band operation. A Manchester encoder combines data output signals into a single aggregate data stream.

Abstract: This invention relates to a switching system testing arrangement which uses a looparound circuit, into which a test signal is injected and received to determine whether the loop is functioning properly. The system provides means for testing individual switches (or equivalent time division counterpart), individual loops and links between switching stages and the network, complete loops between peripherals, short loops between peripherals and their local control units, or any loop that can be set up within the system, without incurring loss of use of parts of the system which would otherwise be required to obtain the loop but are not of interest to test. The control data and test signals are applied, to set up the loop and into the loop respectively, via message transmission paths which are separate from the loop under test.

Abstract: A data communication network comprising ring transmission paths (0,1) interconnecting ring interface nodes (RI1, RI2, RI3) coupled with a node processor and data systems and arranged to propagate data messages along the ring transmission paths between the data systems. Each node is arranged to detect failure of the node to propagate a data message to another node and to flush the data communication network by force reading data messages off the ring transmission paths into the blocked node processor. A node is arranged to automatically maintain and restore operation of the data communication network by loop connecting ones of the ring transmission paths together to isolate segments of the network experiencing trouble and to transfer maintenance and diagnostic data messages between ones of the looped ring transmission paths to restore ring transmission paths and nodes located in isolated segments of the network to service.

Abstract: A data communication system allocates use of a common data communication medium shared by a plurality of stations. During each transmission cycle, the communication medium carries data packets of varying priority which each station receives. The stations are allocated use of the communication medium during one or more priority intervals as a function of the priority of the packet which the station is ready to transmit. Each station is synchronized to a transmission cycle period which is divided into subperiods. Certain types of packets are relegated to transmission and reception within predetermined subperiods.

Abstract: A bus interface for interfacing between a processor and a shared bus is disclosed. The bus interface allows the exchange of data in the form of packets between the bus and the processor. An interface control device exchanges control data with the shared bus (e.g. identification signals, polling signals, control signals) in order to regulate accesses of the interface circuit to the shared bus. State machines (e.g. a transmitter and a receiver) including data pipelines, are responsive to control signals from the interface control device for exchanging data between the shared bus and a data storage device. An access control device both controls the flow of data between the processor and the data storage device and regulates access to the data storage device between the processor and the state machines.

Abstract: A token ring access control protocol circuit which includes an M/T converter for converting incoming serial data in differential Manchester encoded form into transitional encoded form. Next the data is fed into a shift register and held temporarily while it is compared with preset sequences to determine if it is a starting delimiter or an ending delimiter. If a starting delimiter pulse is generated and used to synchronize subsequent circuitry if required. Data from the shift register is continuously sampled with at least a 2 baud delay by a data sample latch circuit which provides and output line for data values and another output line for code violation signals. The data values and code violation values go to a data receiving circuit which processes the data, and loads it onto a local data bus for transmission to other parts of a token ring control system.

Abstract: A network system having a single-wire common signal transmission line for interfacing a serial bit data string between a plurality of data stations connected thereto comprises: (a) first means for repeatedly generating an address information bit signal based on a predetermined time series code for each predetermined synchronization timing, modulating each address information bit signal into a synchronous signal having a frequency which is varied according to a bit status of each address information bit signal, and outputting the modulated synchronous signal to the common signal transmission line so as to superpose on the serial bit data string, (b) second means provided within each station for demodulating the synchronous signal derived from said first means according to the frequency thereof so as to extract the bit status of the address information bit signal, (c) third means provided within each station for reproducing a signal corresponding to the predetermined time series code generated in said first mea

Abstract: Common channel interoffice data transfer circuitry is shown for transmitting and receiving both analog and digital CCIS data. This data transfer circuitry is a data terminal equipment control circuit. The terminal equipment control circuit is microprocessor controlled. The terminal equipment control circuit is adaptable to transfer CCIS data to analog interfaces, such as modems. The circuit is also adaptable to transfer CCIS data to and from digital data sources, such as digital trunks or T1 spans. The design of this circuit possesses a high degree of commonality and, therefore, requires a minimal amount of components.

Abstract: A local area network communication system in which a repeating installation sets a ring number of a ring from which a communication frame was taken out as a source address of the frame. The repeating installation also sets a ring number of a ring to which a communication frame is to be sent. When a station receives the frame, the station checks the source address of the frame to identify the ring number of the ring to which the source station belongs and checks the destination address to identify the ring number of the ring to which the station itself belongs.

Abstract: In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the address of the requested unit are fed to the allocation logic (arbiter) on separate or commonly used lines, thus avoiding idle times during the use of the bus. By evaluating the bus command, the allocation priority can be dynamically changes in order to suppress bus accesses that are bound to fail from the start.

Abstract: An improved method for transmitting messages from the buffers of a bus interface unit participating in a local area network is disclosed wherein the bus interface units are permitted to completely empty their buffers upon each possession of the token and thereby decrease the mean bus waiting time of the network. Further, to optimize network bus waiting time while maintaining an upper limit on BIU service time and thereby guaranteeing each bus interface unit of the network one opportunity to transmit during this upper limit time interval, each bus interface unit of the network monitors the BIU service time to determine when this time reaches the upper limit time interval and, thereafter, limits the quantum of information transmitted from its buffer to thereby prevent the BIU service time from increasing beyond the upper limit time interval.

Abstract: In an information transmission system for use for inter-node trunks, both circuit-switched and packet-switched traffic is handled, the former being given priority. The system uses successive equal-length envelopes each providing a number of bits usable to provide a number of frames each usable for either sort of traffic. Circuit-switched traffic has priority and uses frames at the beginnings of the envelopes, after which packets are handled. The envelope is of such a size that it provides frames for all circuit-switched channels to be catered for, and in most cases the remainder of the envelope can handle packet traffic.

Abstract: A communication method and packet switching network in which self-routing packets are communicated through the network by intra-communication of the packets within stages of the network as well as inter-communication of the packets among stages. The stages each having a plurality of pairs of switch nodes with each pair having an intra-node link between the pair of nodes. Each of the switch nodes comprises input controllers and output controllers. The input controller of a node is responsive to the receipt of a packet for interrogating the address field of the packet to determine the destination of the packet. The input control on the basis of the destination determination commmunicates the packet towards the destination via either an inter-stage link or an intra-node link on the basis of availability of the links and an internal control circuit.

Abstract: A telephone or like telecommunications network is disclosed which has n input highways and m output highways, where n is not less than m, each for the time division multiplex transmission of k channels of data. For selective data transfer between any selected channel of any selected input highway and any selected channel of any selected output highway, a digital, time division switching system is provided which comprises n data memories corresponding respectively to the n input highways, each data memory having k addresses corresponding respectively to the k channels of the corresponding input highway. A control circuit having a control memory causes the data from the input highways to be written sequentially into the data memories and for reading the data memories n times during a preassigned transmission period of each channel on the input and output highways.

Abstract: A communication method and self-routing switching network interconnecting a plurality of interface controllers for communicating packets and circuit switched information via multiple paths within the self-routing switching network. The latter comprises stages of switch nodes that are grouped into pairs. The stages are interconnected by links and each pair of switch nodes shares the same set of input links from the preceding stage. In response to receipt of address information from a destination interface controller transmitted via a link, a pair of nodes determines one of a multitude of paths through the switching network by one of the pair responding to the address information to communicate the address information to the next sequential stage after establishing a path through that particular switch node.

Abstract: Individual data bit streams which have been merged into a telemetry stream are regenerated in their original format and at their original data rates by storing frames of the telemetry streams in a buffer, moving the data bits in the frame buffer which are from each merged individual data bit stream to a corresponding individual data bit stream buffer and forming from each individual data bit stream buffer, an output data stream at the same rate and in the same data format as the corresponding individual data bit stream.