Abstract: An improvement is disclosed for telecommunication PCM time division multiplex switching systems of the type having voice access ports, each with a voice path and a signalling path, and having PCM signalling and voice transmit buses to carry information to a switching network. From the network, PCM voice receive buses carry switched voice information to be demultiplexed, converted to analog form and connected to the voice port. A signalling bus carries information from the switching network to registers. The system is improved to enable it to switch data as well as voice information. A data port is provided to accompany each voice port, and the improved system includes means for multiplexing input data at the port and inserting it on the signalling transmit bus once the signalling portion of a call is completed. A receive data bus connects the signalling receive bus to means for demultiplexing data and presenting it to receive data ports.

Abstract: To effect transfer of messages between data units (1-4, 5-8) a switching network of binary distributors (21-24, 31-38) and concentrators (41-48, 51-54) is used. For each distributor in the network the message is preceded by a respective single data bit which is absorbed in the switching system. Thus at the message destination all addressing bits have been absorbed, only the required message being received. Concentrators have both input paths enabled to their respective output paths except when a message is passing through the concentrator when the non-transmitting path is disabled.Any message arriving at a blocked concentrator is lost. Accordingly an acknowledging system uses a reverse path set up in parallel with the forward path to acknowledge receipt of the message. Alternatively the reverse path may be used to return a message fail indication from a blocked concentrator.

Abstract: An interface for use between an asynchronous bus and a signal processor is disclosed. The interface utilizes both a wraparound receive and transmit memory to ensure coherency with very little processor overhead.

Abstract: Each of a plurality of stored program controlled stations associated with a digital telecommunication network includes: a plurality of clocks and an adjustable oscillator for generating transmission pulses used in a local station and adjacent stations; a phase difference meter for determining, with the aid of a clock selector, phase differences between the pulses of the oscillator and the clock pulses; and a plurality of regulation value generators which are connected via a regulation value generator selector to the phase difference meter. Each generator converts in accordance with a network synchronizing method, determined phase differences to regulation values for regulating the oscillator. The program memories of the stations include reprogrammable selection memories to store control information by which the network synchronizing method is selected and by which the clock selectors and generator selectors are controlled such that the oscillators are synchronized in accordance with the selected method.

Abstract: A framing circuit is disclosed for detecting framing bits in a t.d.m. bit stream having an extended DS1 framing format. The circuit comprises a RAM for storing in respect of each of the 772 time channels the five most recent information bits of the time channel and three other, candidate, bits which represent the likelihood that the particular time channel carries the framing bit pattern. The current and five stored information bits of each time channel are checked to detect the six-bit framing bit pattern. The candidate bits have their value increased or decreased, within predetermined limits, in dependence upon whether or not a phase of the framing bit pattern is detected, and the updated information and candidate bits are stored in the RAM. The modification of the candidate bits in this manner is effected in only every third 772-bit frame. A framing signal is produced in dependence upon the candidate bits.

Abstract: The architecture provides a frame format and procedure for routing messages through a single ring or multi-ring communication system. Stations associated with the exchange of messages are located on the single ring or on different rings of the multi-ring communication system. The rings are connected by bridges to form a local area network. The frame format includes a plurality of control bits positioned within a Routing Information (RI) field, a frame control field and a frame status field. Messages are generated and structured in accordance with the frame format. A group of the control bits, in each message, is set with initial values according to the message type. Thus, different messages are characterized by a different sequence of control bit settings. A routing algorithm analyzes the message and depending on the status of the control bits, the message is processed and ultimately switched to its proper destination.

Abstract: A method and arrangement for controlling a time division switching system including a time multiplexed switch is disclosed. The time division switching system comprises a plurality of time-slot interchange units which connect subscriber sets to the input/output ports of a time multiplexed switch. When a connection is to be established between time-slot interchange units, a central control transmits to the time multiplexed switch a path setup message defining the input/output ports to be connected and the time slot to be used for such a connection. The time multiplexed switch controller responds to the path setup messages by disconnecting existing connections through the time multiplexed switch which potentially conflict with the requested connection, then by completing the requested connection. Accordingly, the switching system operates effectively without requiring separate disconnect messages when connections through the time multiplexed switch are no longer needed.

Abstract: A telephone switching network including a remote line switch that couples digital voice signals from a plurality of subscriber lines onto a lesser number of communications links connected to a central office. The remote line switch also includes an intra-nodal switch that switches telephone calls between subscriber lines connected thereto, so that the digital voice signals for the calls need not be transmitted to the central office for switching. The line switch, on receiving a request from the central office for a termination connection to a called line, determines whether both the calling and called lines are connected to it. If they are, and if the line's classes of service as supplied by the central office permit, the line switch establishes a path through its intra-nodal switch to switch the call.

Abstract: A unipolar pulse communication system exploits the fact that certain computer terminals will react only to information pulses of a specific polarity and remain passive to pulses of the reverse polarity. A device at one end of the system passes pulses unchanged, from a first station of a computer to a single cable at the output of the device. Pulses received from a second station of the computer pass through the same device but are inverted before being passed through to the same cable. At the other end of the cable, all pulses are passed unchanged to a third station, and all pulses are inverted and then passed through to a fourth station. As the third and fourth stations only react to information pulses of a specific polarity, the result of the device is to permit two stations of the computer to be connected to two remote stations using only a single interconnecting cable. The device at either end of the cable may be designed so as to permit the same device to be used at either end of the cable.

Abstract: For switching or, respectively, distributing broadband communication signals in message switching systems, broadband switching matrix networks having crosspoint circuits realized in an ECL technology and which are formed by controllable multiplexers is provided. The controllable multiplexers are mutually interconnected to form multistage crosspoint pyramids respectively exhibiting an outgoing line and a plurality of incoming lines, whereby the controllable multiplexers of a respective plurality of crosspoint pyramids are combined on a chip module. The chip module may be a master slice module. An additional transfer crosspoint in the form of a 2-bit multiplexer can be provided at the tip of the pyramid at each crosspoint pyramid, the additional transfer crosspoint also being connectible to the pyramid chip of a further crosspoint pyramid in order to therefore introduce a corresponding expansion of the switching matrix network.

Abstract: Flow control of data packets through a packet switching network to reduce congestion is controlled by an adaptive preferential permit packet (APP) processing from an orginating data terminal through each packet switch node of the network to a destination data terminal. APP requires less buffer storage capacity at each switch node, and enables data packets to enter the network only when there is a permit packet indication that the data packets are likely to reach, and be accepted by, their destination. The permit packet is sent node to node (16-19, 25, 28) prior to a transmission of a bulk of data packets. Each node is equipped to queue buffer (12-15, 21-24) a permit packet on a preferential basis ahead of data packets. The node discards the permit packet if the number of packets awaiting transmission from that node exceeds a prescribed threshold. This is throttling process, since the originating port times out and resends a permit packet if a permit-return packet is not received within a predetermined time.

Abstract: A digital signal multiplex device has at least one multiplexer and at least one demultiplexer for pulse frames having a number of useful information channels. The transmitter has a data protection coder and the receiver has a data protection decoder. The data protection coder generates an error protection code and inserts the error protection information into one or more of the useful information channels or into whole-numbered portions of at least one useful information channel in the pulse frame. At the receiving end, the error protection information-containing portion of the signal is supplied to the data protection decoder, which recognizes and corrects errors in all or certain of the channels of the transmitted time division multiplex signal. In this manner, all or individual ones of the useful information channels, which may be utilized for data transmission, can be transmitted with a lower bit error quota without departing from the standardized hierarchy stages of data transmission systems.

Abstract: An integrated digital network (IDN) includes a matrix and user signal ports for exchanging voice, data, IDN control, and building control digital signals between the matrix and user equipment, the digital signals comprising single samples of each signal type from each user port in each IDN sample time interval, the IDN further including a transmission system for concentrating user port digital signal samples of each sample time interval, by common signal type, into multiple bit channel signals for exchange between the user ports and matrix signal ports of the matrix switch, the matrix switch interconnecting each channel signal from one or more user ports to one or more other user ports.

Abstract: A data transmission system that can controllably transmit data in three different modes between connected data devices. The first mode transmits data at a 64 Kbps rate. The second mode transmits data at a 56 Kbps rate plus control signals at an 8 Kbps rate. The third mode transmits data and control messages at a rate of up to 50 Kbps between connected terminals or other data devices. For all modes, the data is transmitted by inserting it one byte at a time into an information field of successive ones of cyclically reoccurring time multiplexed frames.

Abstract: During algebraic summing of code words from conference participants to form a partial sum-code word overflow of the values may occur. Such an overflow can be prevented when prior to the adding operations the numerical range is extended and an adjustment of weighting factors is effected in dependence on the measured speech intensity of the partial sum-code word. By multiplying by these (attenuation) factors the outgoing subscriber-code word is mapped again on the original numerical range in the attenuation circuit. To reduce a noise level originating, for example, from line interferences, quantization errors, etc. subscribers which are currently not speaking can be attenuated in a further attenuation control circuit of the conference arrangement.

Abstract: The disclosed digital conference circuit additively combines conference signals with a single adder, a partial sum accumulator RAM, and conversion ROMs. Internal conferencing time slots are dynamically assignable via a microprocessor controlled channel indexing memory. The signal level on lines can be selectively adjusted to compensate for loop attenuation on a per-line basis. The circuit can operate with a number of voice coding law PCM signals from CODECs by the use of conversion ROMs containing conversion tables for the selected voice coding law. Additive background noise levels may be reduced by the dynamic selection of modified sections of the conversion tables. The number of conferences available and the number of lines per conference is limited only by the number N of internal conferencing PCM time slots. The number of internal conferencing time slots used per conference equals the square of the number of lines in the conference.

Abstract: A loop type data transmission system based on a token pass principle, wherein a station whose transmission of data is completed passes therethrough a token to the stations located downstream. The station demanding the transmission acquires the right of transmission when received the token, to perform data transmission with a given station. The token signal is classified into a free token representative of the freedom of the line and a busy token representative of occupation of the line. Among a plurality of stations, only one station is destined to execute detection of transmission failure and remedy thereof. This one station is adapted to convert the free token detected upon reconstitution and repeating of the received information into the busy signal and subsequently re-send the free token. The station having sent out the free token after the completed data transmission is transferred to the state for reconstituting and repeating the received information when the busy token returns to that station.

Abstract: Half-duplex switched carrier operation is emulated in a full-duplex voiceband data transmission system by utilizing predetermined signal indications in each channel to signal the initiation and termination of user data in that channel and thus to control the Receive Line Signal lead extending to the terminals at respective ends of the transmission channel. The signal indication which signals the initiation of transmission is illustratively two scrambled spaces inserted into an idle-state sequence of continuous scrambled marks. The signal indication which signals the termination of transmission is illustratively a stream of 65 unscrambled marks.

Abstract: The disclosed data communication equipment (DCE) provides full-duplex, split-speed data communication over 2-wire dial-up telephone circuits, typically between a host processor and data terminal equipment (DTE). A telephone line interface includes low speed and high speed modems that establish a low-speed DTE-to-Host communication channel and a high-speed Host-to-DTE communication channel for split-speed full-duplex data communication. An I/O interface interfaces the DCE to the Host/DTE I/O ports at selectable asynchronous I/O speeds (typically symmetrical). A communications processor provides buffering and control functions, and implements split-speed data communication in accordance with the high-speed and low-speed communication protocols. In addition, the communication processor provides data compression for the high-speed channel, and error checking and retransmission for both the high speed and low speed channels. The DCE telephone line interface network is switchable between Host and DTE modes.

Abstract: A method for the examination of an internal interconnection system between n terminals of an electrical network and for storing the results in a memory comprising n memory cells by means of measuring the existence or non-existence of the signal passage between the terminals, in which a demultiplexer is used to pass a marking state on a terminal of the network and a multiplexer is used to detect the throughpass of the marking signal to other terminals of the network in first cycles a, and when such passage is detected, the positions of the demultiplexer and the multiplexer are stored together with a so called closing bit representing the end of a series of interconnections, and in subsequent cycles b the next undetected terminal is determined which is followed by a next cycle a, and this sequence is continued until all interconnections of the network get stored in the memory.