Abstract: A new and improved shifter circuit for multiplexing bytes of data into various orders on a finite size bus is disclosed. The improved shifter circuit includes an array of barrel shifter circuits arranged into N groups of M shifter circuits per group wherein each shifter circuit has P data input terminals and P output terminals. The letters N, M and P represent integers. Each of the P output terminals of each of the M shifter circuits in a group are coupled to one another, respectively, so as to form N.times.P output terminals of the array.

Abstract: A communication method and digital multi-customer data interface for interconnecting a number of customer terminals to a main packet switching network of a local area data transport system that provides data communication services such as interactive video text service between data service vendors and customers. The digital multi-customer interface utilizes a main processor, control circuit, and multi-customer protocol controller to implement the protocol functions for the communication of packets and control information over individual serial transmission paths. The multi-customer protocol controller comprises a control processor and a formatter circuit for synchronously communicating packets for a plurality of customer terminals via customer line units and customer lines. The control processor performs byte-to-packet and packet-to-byte functions between the main processor and the formatter circuit.

Abstract: A system for the digital conversion of a time division multiplex signal into a frequency division multiplex signal wherein the signals of the individual time multiplex channels are filtered by means of bandpass filters, their sampling rates are increased by the factor N to fA and the output signals of these bandpass filters are combined, by means of a summing member, into the frequency multiplex signal, and/or a system for the digital conversion of a frequency multiplex signal into a time division multiplex signal, wherein the digitalized frequency multiplex signal is divided by means of respective bandpass filters into the signals of the individual frequency multiplex channels and their sampling rate fA is reduced by the factor N. The individual bandpass filters (BP) are designed as recursive filters having the transfer functionH(z)=U2(z)/U1(z)=P(z)/Q(z.sup.N)where U1(z) and U2(z) represent the filter input and filter output spectra respectively, z=e.sup.j2.pi.f/fA, and f is the signal frequency.

Abstract: This invention provides a digital data communication system which is able to combine two data streams from two data sources at the transmitter end, transmit the data and then separate the streams to two data ports at the receiver end. The system makes use of QAM or PSK modulation, and synchronization between the transmitter and the receiver is maintained by changing the radial component of every other transmitted symbol. At the receiver end the radial components of every other symbols are correlated to detect loss of synchronization. Once such a loss is detected, the receiver is adapted to self-synchronize itself with the transmitter.

Abstract: A reconfigurable serial loop or ring communication system is provided with a method and apparatus which enables stations on the loop to ascertain the address of its nearest active upstream neighbor (NAUN). A Ring Poll Frame is generated and broadcast from an originating station. The Ring Poll Frame includes a Ring Poll command, a From Address and a reset Address Recognized (AR) control bit. The first active downstream station recognizes the command with the control bit in the reset state, copies the contents of the ring poll frame and sets the bit. The set bit inhibits subsequent downstream stations from copying the frame. The first active station then generates a substantially similar formatted ring poll frame and passes it downstream. The process is continued by downstream active stations until the originating station receives a ring poll frame having a reset control bit. The reset control bit is an indication that all stations on the loop know the address of its NAUN.

Abstract: A signal retransmission control circuit for stations of a multi-station digital communications network interconnected in a time division manner through a communication cable. The retransmission control circuit detects signal collisions when two or more stations simultaneously transmit their signals and in response to this detection of signal collision initiates a signal retransmission waiting time, during which the signal cannot be transmitted. The control circuit further includes a waiting time adjustment means for increasing the waiting time if another station begins signal transmission during a waiting time period.

Abstract: In order to enhance the general purposeness of a time domain multiplexer for digital channel signals of unequal bit rates, the time domain multiplexer is constructed of a plurality of channel units which provide information signals and bit rate signals of input channel signals, a plurality of logic circuits which multiplex the information signals from the channel units, and a control circuit which selects and combines the logic circuits in accordance with the bit rate signal so as to construct a multiplexer conforming with the bit rate.

Abstract: A data communication device for use either as an interface between a data processing device and a transmission medium of a CSMA/CD network or as a repeater between a CSMA/CD network and an additional data communication network which shares a transmission medium with the CSMA/CD network, sends an obstruction signal towards the CSMA/CD network when an input buffer tends to overflow on storing an input data packet for delivery to the data processing device or for transmission towards the additional data communication network. The obstruction signal is for causing a collision in the CSMA/CD network. The additional data communication network may be plural in number. When the additional data communication networks are CSMA/CD networks, the transmission of data packets thereto is suspended when a collision is detected at the repeater. The transmission is restarted a variable interval after disappearance of the collision. The variable interval corresponds to a weighted random number known in the art.

Abstract: Bidirectional communication upon a high performance synchronous (25 MHz line transfer rate) parallel digital communication bus interconnecting large numbers (up to 256 along 1 meter of bus) of very large scale integrated (VLSI) cirucit devices is supported by VLSI wired-Or driver/receiver (D/R) circuit elements synergistically operative under a two-time-phase bus electrical protocol for bus drive. During a first phase of approximately 10 nanoseconds all interfacing driver circuits additively drive, or pull-up, connected bus lines to a +3 v.d.c. logical High condition. During a second phase of approximately 20 nanoseconds during each 40 nanosecond cycle time D/R circuits present high impedance to charged bus lines for maintenance of such logical High and transmission of a logical "0", or else one or more D/R circuits drain line charge toward 0 v.d.c. for transmission for a logical "1". Two point driver to receiver, wired-OR, broadcast, and/or eavesdrop communication are supported for bus lines.

Abstract: There is disclosed a general purpose linear time division multiplexed conference system for continuously summing and supplying digital message samples arriving in time slots within a frame. The conference system integrates both voice and data network conference connections and provides total isolation between the secondary legs of a data network connection. The host computer of a data conference connection is assigned to the lowest ordered time slot relative to the time slots assigned to secondary legs of the data conference connection. The summation of data samples accumulated from each leg of the data conference connection during a write cycle is modified during a next supply cycle after distribution to the host computer but prior to distribution to secondary legs. Modification is achieved by overwriting the summation with the data sample received from the host computer during the prior write cycle.

Abstract: Messages, comprising a plurality of multiplexed packets of information bits, are received on a transmission line from each of a plurality of sources. All packets from the same source have the same source identification number and are stored in one of a plurality of first-in, first-out queues. After at least one of said packets has been stored, it is available for being read out from the first-in, first-out queue. In order to insure that each queue has an equal chance of being accessed by a utilization means, the status of all queues is registered in a status register.

Abstract: A group of terminal units (GUT) for a digital exchange having distributed control residing in control means comprising microprocessor control units (UC) which are interconnected by means of the exchanges' time switching network (RXA to RXD). The control units UC are connected to each other by a duplicated point-to-point link (RIT1, RIT2) and to the switching network by a coupler (AM) which is provided with a send/receive circuit that operates using a semaphore procedure. Each of the terminal units (UT) includes a control microprocessor (mp) connected to the switching network by a send-receive circuit (ER) using a semaphore, or question and answer, procedure. The terminal units (UT) are controlled by the control units (UC) by interchanging messages using a common procedure for all the terminal units. These messages are interchanged over channels in the links that make up the switching network of the exchange.

Abstract: A local communication network for interconnecting data transmitting and receiving stations, such as computers. A number of stations are connected for transmission of data onto an outbound unidirectional bus and are connected to receive data from an inbound bus in series with the outbound one. A "locomotive" generator transmits locomotives onto the outbound bus, and each station, if ready to transmit, adds a packet of data to the next passing "train" led by a locomotive. The resulting efficiency is relatively high and the network delay is relatively low, these figures being even further improved by the use of multiple locomotive generators or a regular-interval locomotive generator. Other embodiments employ an open-ring configuration, and a star coupler to minimize inbound losses.

Abstract: A tone source is automatically adaptable in operation to generate tones as required for virtually any TDM telephone system in accordance with stored tone samples being defined to meet the requirements of a particular one of the telephone systems. The tone source provides encoded tone samples from a ROM wherein each tone sequence is stored at corresponding sequential address locations. Each sequence is terminated at unique first and last address locations. The last address location is followed by an address location having an end-of-tone code stored therein. A sample of each of the tones is progressively fetched from the ROM in response to each frame occurrence in an associated operating telephone facility. The first address of each sequence is stored at a corresponding index address location in the ROM. In response to each end-of-tone occurrence the index address of the instant tone sample is read from the ROM and used as a starting point for subsequent fetches.

Abstract: A time divided digital signal transmission system includes a transmitter for converting plural analog signals to digit signals, generating multiplexed time divided signals from the digital signals, and transmitting the multiplexed time divided signals by a digital data transmission circuit. The system further includes a receiver for receiving the multiplexed time divided signals, demultiplexing the multiplexed time divided signals so as to thereby obtain the original digital signals and converting the original digital signals back into the original analog signals. The system is arranged to effectively utilize both synchronizing signals and clock signals for the analog to digital conversion and the digital to analog conversion in the system.

Abstract: A signal distribution signal for a time-division exchange has a distributed control architecture. Its switching network is organized as a plurality of independent planes (RXA to RXD) with terminal units (UT) and control units (UC) are connected via multiplex links (MX) and are synchronized by a time base (BDG) via clock signal distribution modules (MD). Each terminal or control unit is connected both to the switching network and to the clock signal distribution means by at least two independent parallel connections (F1, F2) each of which comprises multiplex links (MX) connected to different planes of the switching network, and at least one distribution link (D) connected to a different distribution module (MD) for each of said parallel connections connected to a given unit. Such exchanges are used for telecommunications purposes.

Abstract: A conference circuit in a digital telephone switching system includes a first code converter (CCL), which converts nonlinearly coded speech samples into linearly coded speech samples, and adder (ADD), which sums the converted speech samples originating from the participants in the conference, and a second code converter (LCC), which reconverts the sum values into nonlinearly coded speech samples. To avoid distortion without increasing the insertion loss, the speech samples of the individual participants are integrated with respect to time and compared in an evaluation circuit (EVC). The speech samples of the loudest participant are fed to the adder unattenuated, while those of all other participants are attenuated by a predetermined value before being added.

Abstract: In a time division multiple access system comprising a central station and a plurality of substations, a subsidiary analog signal is sampled at a sampling circuit of each substation M times during each frame period to produce a succession of sampled pulses. A group of M sampled pulses is located by a substation delay circuit in each up-link burst assigned to each substation. Responsive to an up-link succession including each up-link burst, the central station reproduces the sampled pulse group from each up-link burst into a reproduced group of M reproduced pulses by central station sampling pulses synchronized with the M sampled pulses. The M reproduced pulses are rearranged by a central station delay circuit into sampled pulse reproductions appearing M times in each frame period. The sampled pulse reproductions are desampled into the subsidiary signal. The number of M may be equal to or greater than one.

Abstract: A multiplexer comprises a select circuit having a plurality of OR gates responsive to digital select signals. Transistors within the OR gates are collector dotted and provide a plurality of select circuit outputs to a plurality of AND gates which are also responsive to a plurality of input signals. The collector dotting of the four OR gates of the select circuit provides a multiplexer having a single gate delay of data transmission. The multiplexer consumes less current by having only a single current source for the AND gates.

Abstract: Digital telephone exchange comprising a plurality of peripheral control domains PCD which are either connected to a digital trunk network DTN or are directly interconnected. Each domain comprises several digital subscriber interface units DSI, a group of digital subscriber sets SS being connected to each interface unit.The transmission of information over the subscriber line is effected in a b-channel for speech (64 kb/s) a b'-channel for circuit-switched data (0/8/64 kb/s) and a .DELTA.-channel for packet-switched data (8/16 kb/s).The subscriber line interface circuits SLIC comprise means (166) for identifying the packet-switched data signals and to apply them to a packet processing unit PPU. In this unit the packets are distinguished as firstly signalling information (s) and secondly telemetry and slow data (t+d').