Abstract: A network for selectively switching channels from n incoming PCM links to as many outgoing PCM links comprises two sections of a receiving-side stage with n input terminals each, connected in parallel to respective incoming links, and with m output terminals working into an intermediate stage with 2m input terminals and as many output terminals. The latter are connected to respective input terminals of two sections of a transmitting-side stage with n output terminals each; homologous output terminals of the two transmitting-side sections are alternatively connectable to respective channels of n outgoing PCM links by means of multiplexers which are switched by a logic unit under the control of a processor also detecting possible malfunctions in any section. Each stage consists of a multiplicity of temporal or spatial switching matrices.

Abstract: A method for use in a local loop network comprising a plurality of stations which are distributed along a bus, each station being connected to the bus via a coupler which is inserted in the bus. The time-locking method for these stations comprises a transmission phase during which a looping unit which is also inserted in the bus transmits a frame (transmission frame) which consists of a synchronization word and one or more slots which initially do not contain data and which correspond to the time position occupied by each of the stations, a receiving phase during which the demodulation of the transmission frame by the master clock of the looping unit is performed after the retransmission in the form of a frame which is referred to as the receiving frame, of this frame to the coupler of each of the successive stations and, after the receiving phase, new transmission and receiving phases until the insertion of the data on the bus by each station during a transmission phase takes place with the desired accuracy.

Abstract: The CCITT has given recommendations for two types of hierarchies of PCM multiplex systems for telephony transmission: a first type based on a first-order PCM multiplex system having a nominal bit rate of 2048 kbit/s for 30 telephone channels while employing the A-law, and a second type based on a first-order PCM multiplex system having a nominal bit rate of 1544 kbit/s for 24 telephone channels while employing the .mu.-law.The fourth-order digital multiplex system in accordance with the invention comprises a transmitter (1) having a digital multiplexer (7) arranged for cyclically bit-wise interleaving three digital signals having nominal bit rates of 44 736 kbit/s, the third order in the second type of PCM multiplex hierarchy, into a composite digital signal having a nominal bit rate of 139 264 kbit/s, the fourth order in the first type of PCM multiplex hierarchy, and having a specific frame structure (a in FIG.

Abstract: This invention discloses a demultiplexer with a first memory element for storing received data bits, a second memory element having individual cells connected to individual remote units (i.e. parallel output) and a logic unit for transferring the appropriate bits from the first to the second memory element in accordance with the received signal configuration. The enabling signal for the second memory element is derived from the demultiplex sync signal.

Abstract: An aligner with a time switching capability is disclosed. The aligner has a store for storing incoming data. The store is sufficiently large that it can hold more than one frame of information. Data is written into the store under the control of clock signals associated with the incoming data. Data is read from the store under the control of a local clock. Read addresses are generated by a unit which is so arranged that if a clash between the current write address and the generated read address is sensed to be imminent, reading of the corresponding address in the previous or subsequent frame occurs. Thus, the aligner can operate as a time switch and clashes between reading and writing are avoided by allowing slippage of one frame.

Abstract: In a receiver for multiplexed QAM/PSK signals which have been radial amplitude modulated for synchronization, an error signal is generated by each received signal to the corresponding ideal point as mapped in the complex plane. A synchronizing signal is generated and synchronized by the error signal and is used for both demultiplexing, and amplitude demodulating the signal.

Abstract: This disclosure concerns a communications network information system, and ovides apparatus and a method for efficiently providing survivable communications capability to every surviving node in the communications network from every other surviving node. The types of information provided can include high priority message between users of the communications system, or perhaps of even greater importance, very frequently updated status information about the communications network nodes and their interconnecting links for use in optimally utilizing the surviving resources of a heavily damaged network. With this capability every surviving node in the network will be automatically and efficiently provided with the status of every node and interconnecting link.

Abstract: The structure of an access point to a data packet broadcasting network comprises a plurality of couplers (Cx), a buffer memory (MTP) and a central control unit (MPC) interconnected by a main bus (MB). Each coupler (Cx) is connected to a plurality of data sources. The buffer memory (MTP) is connected to a transmission equipment of the data packet broadcasting network. Each coupler (Cx) includes a dual access (MCx), a microprocessor (MUPx), a read only memory (ROMx), a plurality of access circuits (CAS1-CAS4 and CAP1-CAP4) each connected to a data source, a local bus (Bx). In each coupler there is stored, in addition to the coupler control software, a set of subroutines for exchanging information with the buffer memory (MTP).

Abstract: In a digital signal transmission system for effecting time-division multiplexing/circuit switching transmission of data in the form of packets by means of transmission cable, a method for the synchronization of system timing which permits the establishment of system timing such as the synchronization of frames and blocks is improved.For this purpose, all of the individual personal stations in the transmission system have their own respective distance codes, and only the master station incorporates the distance code of transmitting personal station in its master packet, and the other personal stations than the master station independently calculate their own timing for sending out packets on the basis of the aforementioned data to establish their own system timing.

Abstract: A multichannel duplex radio system for cordless telephone in which digital information is sent between the two ends. The data is divided into blocks which are transmitted in a fraction of the original block length. The other time slots are used for the duplex return path and for other similar equipment operating nearby. A direct conversion radio receiver is used in which the local oscillator signal is modulated for transmission.

Abstract: A fast circuit switching system that establishes a circuit for each packet-sized data communication. Information is conveyed from a number of communications modules in source channels to a number of port controllers and to a network. Information is conveyed from the network to destination channels. Each communications module includes a transmitter that transmits in an associated source channel, circuit setup request signals defining destination channels and also transmits data. Each port controller stores one of a number of status words defining the availability of the destination channels and each of these status words is cycled to each port controller. A port controller responds to one of the circuit setup request signals and to subsequent data, when one of the status words cycled thereto defines as available, a destination channel defined by the circuit setup request signal, by transmitting the circuit setup request signal and the subsequent data to the network.

Abstract: A fast circuit switching system that establishes a circuit for each packet-sized data communication. A time-slot interchanger included in the system network has a sequential access, circulating control memory, the contents of which can be rapidly and frequently changed with minimal impairment of time-slot interchanger throughput. Such changes are effected by controlling the transmission of information concerning established connections, from a control memory output register to a control memory input register and by controlling the transmission of information concerning new connections, to the control memory input register.

Abstract: A time division switching system having a time-space-time architecture is disclosed. The time-multiplexed communication links of this system comprise a plurality of channels certain of which are used to convey control information and the remaining ones of which are normally used to convey digital representations of subscriber signals. When a large quantity of control information must be exchanged, the system preempts selected channels from conveying digital representations of subscriber signals and uses these preempted channels to convey the large quantity of control information.

Abstract: A digital transmission system employing nBmB codes in which provision is made for insertion of service and auxiliary data bits. The transmitter of the transmission system includes a series to parallel converter, register file, pulse insertion circuit, nBmB encoder and parallel to series converter. The bit rate of the parallel n bit code streams is converted to produce an additional time slot after each occurrence of a predetermined number of data bits. Service and auxiliary data bits are inserted in the additional time slots. The receiver portion of the transmission system includes a series to parallel converter, followed by an nBmB decoder, a pulse separator, a register file and a parallel to series converter. At the receiver, the mB code is converted back to an nB code from which the service and auxiliary data bits are extracted and subsequently removed.

Abstract: In a bus communication system, a unidirectional transmit bus is coupled to a unidirectional receive bus such that information packets leaving the transmit bus are placed on the receive bus. A plurality of bus interface units (BIUs) are coupled in series at spaced locations to the transmit and receive buses. The BIUs communicate with one another by transmitting information packets on the transmit bus and receiving transmitted information packets from the receive bus. A BIU transmits an information packet when both buses are silent. In the event of a collision between two information packets, downstream BIUs abort transmission and defer to the most upstream BIU having transmitted. Each BIU having had a transmission aborted attempts to gain access to the bus by placing a beep on the transmit bus which informs other BIUs that a BIU requests access to the bus. Only the most upstream BIU requesting access is permitted to transmit a packet.

Abstract: A remote data link controller is disclosed for formatting, transmitting and receiving control data over high speed digital data links between the peripheral processors of a plurality of telecommunications switching systems. The remote data link controller includes a microprocessor controlled data link processing circuit which is time shared among all of the digital data links. The remote data link controller processes one transmit and one receive message byte during a reformatting cycle for each digital data link. It stores any intermediate results in a temporary memory than proceeds to service the next digital data link. The remote data link controller fetches intermediate results from the temporary memory, processes the data and stores the next intermediate results in the temporary memory until it has completely serviced all of the digital data links.

Abstract: A bit compression coding circuit incorporates signaling bit insertion. An input signal sample(s) representing, for example, PCM encoded speech or voiceband data, is delivered to a difference circuit (31) where a predicted signal (s.sub.e) is subtracted from it. The predicted signal is an estimate of the input sample derived from a predictor (32). The resultant difference signal is coupled to the input of an adaptive quantizer (34) which provides at its output a bit compressed quantized differential PCM version of the difference signal. A multiplexer (37) receives the output of the quantizer and serves to periodically preempt the least significant bit of the bit compressed PCM signal and substitute a signaling bit therefor. The output of the multiplexer is coupled to the input of an adder (38) wherein it is added to the predicted signal.

Abstract: A multistation digital communication network of the type wherein station packet signals are transmitted during periodically repeated block times, a plurality of blocks forming a frame, each block time repeating once per frame, the first block of a frame being the master block. Multiple, contiguous empty blocks within a single frame are produced by locating all signal carrying frame blocks and packing them one against the other beginning with the master frame, to thereby form multiple, contiguous signal carrying or used blocks beginning from and including the master block. The remainder of the frame blocks are then contiguous empty blocks capable of receiving new packet signals, several blocks in length. Each station of the multistation network is provided with circuitry for accomplishing the block packing technique and for determining the first and last contiguous empty frame blocks.

Abstract: In a TDMA network wherein a central station sends signals towards satellite stations in downward frames (A), each comprising a control time slot (Td0) and speech time slots (Td1 to TdM), and receives signals from one to M satellite stations in upward frames (C) of a like format, the central station checks the number of idle time slots in each of the downward and upward frames. Only when the number exceeds a preselected number, one of the idle time slots is selected as an adjustment time slot. The ordinary number given to the adjustment time slot is transmitted in a number field (Nf) of the downward control time slot. Each satellite station generates a time axis indicative of local time slots (D) with a delay relative to the thereby received downward time slots (B). On adjusting the time axis in a selected satellite station, the station sends a short burst (t.sub.s) in the local time slot indicated by the received number field.

Abstract: A digital time-divison switch comprising a multiplexer which multiplexes digitalized voice signals, supervisory signals transmitted from line circuit portions, and so forth, and which inserts these signals into predetermined time slots. The digital switch also includes a signal-extracting circuit which extracts the supervisory signals from the time slots assigned for control signals and which transmits the extracted supervisory signals to a common control unit through the supervisory signal receiver, a switching network which switches data time slots, a signal inserting circuit for transmitting control signals to the line circuit portions, and a distributor circuit for distributing the voice signals and so on to each line circuit.