Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.

Abstract: An object of the present invention to provide a highly reliable semiconductor device. Another object is to provide a manufacturing method of a highly reliable semiconductor device. Still another object is to provide a semiconductor device having low power consumption. Yet another object is to provide a manufacturing method of a semiconductor device having low power consumption. Furthermore, another object is to provide a semiconductor device which can be manufactured with high mass productivity. Another object is to provide a manufacturing method of a semiconductor device which can be manufactured with high mass productivity. An impurity remaining in an oxide semiconductor layer is removed so that the oxide semiconductor layer is purified to have an extremely high purity. Specifically, after adding a halogen element into the oxide semiconductor layer, heat treatment is performed to remove an impurity from the oxide semiconductor layer. The halogen element is preferably fluorine.

Abstract: A first switching element and a second switching element are thermally connected to each other since the first switching element and the second switching element are fixed on a second substrate. An upper arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element. The lower arm is capable of increasing the current capacity of the semiconductor device because of the parallel connection of the first switching element and the second switching element.

Abstract: The present disclosure relates to a solid-state image sensor and an electronic device enabling prevention of entrance of incident light from adjacent pixels and suppression of color mixture, decrease in resolution, and decrease in sensitivity. In a solid-state image sensor according to one aspect of the present disclosure, each pixel includes: these different photoelectric conversion parts configured to perform photoelectric conversion of light of a first wavelength of light of a second wavelength and a third wavelength respectively. An electrode wiring provided at a boundary of adjacent pixels, horizontally connects an electrode of at least one of the photoelectric conversion parts in one of the adjacent pixels with an electrode of the corresponding one of the photoelectric conversion parts in another of the adjacent pixels and vertically connects with an electrode of at least one of the photoelectric conversion parts of each of the pixels.

Abstract: Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer, a base film layer, and a seed layer. A patterned mask is formed with a heat spreader opening and via openings. Vias and a heat spreader may be formed in the pattern mask openings at the same time using a plating process and a die attached to the head spreader by a die attachment layer. A molding compound is applied over the die and heat spreader so that the heat spreader is disposed at the second side of the molded substrate. A first RDL may have a plurality of mounting pads and a plurality of conductive lines is formed on the molded substrate, the mounting pads may have a bond pitch greater than the bond pitch of the die contact pads.

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a semiconductor substrate in which a multi-depth trench is formed, the multi-depth trench including a shallow trench and a deep trench arranged below the shallow trench, a first dielectric material formed in partial area of the multi-depth trench, the first dielectric material including a slope in the shallow trench that extends upward from a corner where a bottom plane of the shallow trench and a sidewall of the deep trench meets, the slope being inclined with respect to the bottom plane of the shallow trench, and a second dielectric material formed in areas of the multi-depth trench in which the first dielectric material is absent.

Abstract: An organic electroluminescence device according to one aspect of the present invention includes: a base material having a top surface on which a recess is provided; a reflective layer provided along at least a surface of the recess; a filling layer filled inside the recess via the reflective layer, the filling layer having light transmissivity; a first electrode provided at least on an upper layer side of the filling layer, the first electrode having light transmissivity; an organic layer provided on an upper layer side of the first electrode, the organic layer including at least a light emitting layer; and a second electrode provided on an upper layer side of the organic layer, the second electrode having light transmissivity, wherein a coloring material is mixed into the filling layer.

Abstract: A static random access memory unit structure and layout structure includes two pull-up transistors, two pull-down transistors, two slot contact plugs, and two metal-zero interconnects. Each metal-zero interconnect is disposed on each slot contact plug and a gate of each pull-up transistor, in which, each slot contact plug crosses a drain of each pull-down transistor and a drain of each pull-up transistor and extends to cross an end of each metal-zero interconnect. A gap between the slot contact plugs is smaller than a gap between the metal-zero interconnects.

Abstract: A stacked image sensor includes: a lower device including a lower inter-layer dielectric layer over an upper surface of a lower substrate, and a lower capping layer over the lower inter-layer dielectric layer; an upper device stacked over the lower device, including photodiodes in an upper substrate, an upper inter-layer dielectric layer below a lower surface of the upper substrate, and an upper capping layer below the upper inter-layer dielectric layer; and an air gap formed between the lower inter-layer dielectric layer and the upper inter-layer dielectric layer.

Abstract: Some embodiments include a conductive structure which has a first conductive material having a work function of at least 4.5 eV, and a second conductive material over and directly against the first conductive material. The second conductive material has a work function of less than 4.5 eV, and is shaped as an upwardly-opening container. The conductive structure includes a third conductive material within the upwardly-opening container shape of the second conductive material and directly against the second conductive material. The third conductive material is a different composition relative to the second conductive material. Some embodiments include wordlines, and some embodiments include transistors.

Abstract: An electric-programmable magnetic module comprising a micro electro mechanical system (MEMS) chip and a bonding equipment is provided. The MEMS chip comprises a plurality of electromagnetic coils and each of the electromagnetic coils is individually controlled. The MEMS chip is assembled with and carried by the bonding equipment.

Abstract: Some embodiments relate to an integrated circuit (IC) disposed on a silicon substrate, which includes a well region having a first conductivity type. A dielectric layer is arranged over an upper surface of the silicon substrate, and extends over outer edges of the well region and includes an opening that leaves an inner portion of the well region exposed. An epitaxial pillar of SiGe or Ge extends upward from the inner portion of the well region. The epitaxial pillar includes a lower epitaxial region having the first conductivity type and an upper epitaxial region having a second conductivity type, which is opposite the first conductivity type. A dielectric sidewall structure surrounds the epitaxial pillar and has a bottom surface that rests on an upper surface of the dielectric layer.

Abstract: After forming a trench extending through a sacrificial gate layer to expose a surface of a doped bottom semiconductor layer, a diode including a first doped semiconductor segment and a second doped semiconductor segment having a different conductivity type than the first doped semiconductor segment is formed within the trench. The sacrificial gate layer that laterally surrounds the first doped semiconductor segment and the second doped semiconductor segment is subsequently replaced with a gate structure to form a gated diode.

Abstract: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.

Abstract: An oxide semiconductor TFT substrate includes a substrate, a gate and a first heavily doped transparent conducting layer formed on a substrate and covered by a gate isolation layer. An island shaped oxide semiconductor layer and an island shaped etching stopper layer are sequentially formed on the gate isolation layer with two side parts of the oxide semiconductor layer exposed outside the etching stopper layer. A source and a drain are formed on the two side parts of the oxide semiconductor layer to be in electrical connection therewith with a heavily doped transparent conducting layer therebetween. A protecting layer is formed on the source and the drain and is formed with a via. A pixel electrode extends through the via to electrically connect to the source and the drain with a heavily doped transparent conducting layer interposed therebetween and in direct contact therewith.

Abstract: A method includes performing one or more times of a sequence and reducing a film thickness of a fluorocarbon-containing film formed by performing one or more times of the sequence. Each of the one or more times of the sequence includes forming the fluorocarbon-containing film on a processing target object by generating plasma of a processing gas containing a fluorocarbon gas and not containing an oxygen gas; and etching a first region with radicals of fluorocarbon contained in the fluorocarbon-containing film. In the method, an alternating repetition in which the one or more times of the sequence and the reducing of the film thickness of the fluorocarbon-containing film are alternately repeated is performed.

Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.

Abstract: A semiconductor component support is provided which includes a component support portion for a semiconductor component to be mounted on the semiconductor component support portion. The component support portion includes a metal part that includes an opening in plan view. The opening of the metal part includes first and second sections. The second section communicates with the first section, and is arranged outside the first section. The second section is wider than the first section. The first section can be at least partially positioned directly under a mount-side main surface of the semiconductor component.

Abstract: A junctionless field-effect transistor is provided and has an ultra-thin low-crystalline silicon channel. A fabrication method thereof also is provided for enabling greatly improved economics by significantly reducing the process costs while having electrical characteristics similar to those of the one formed on an SOI substrate by source/channel/drain regions formed in a junctionless ultra-thin low-crystalline silicon layer that has lower crystallinity than that of single-crystal silicon and that has a thickness of 20 nm or less on a bulk silicon substrate instead of an expensive SOI substrate.

Abstract: An organic light-emitting device includes an anode, a cathode, and an organic layer between the anode and the cathode, wherein the organic layer includes a mixed organic layer, and the mixed organic layer includes at least two different compounds, and a triplet energy of at least one compound of the at least two different compounds is 2.2 eV or higher. The organic light-emitting device according to embodiments of the present invention may have a low driving voltage, a high efficiency, and a long lifespan.