Abstract: Semiconductor arrangements and methods of manufacturing the same. The semiconductor arrangement may include: a substrate including a base substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer; first and second fin structures formed on the substrate and extending in the same straight line, each of the first and second fin structures including at least portions of the second semiconductor layer; a first isolation part formed around the first and second fin structures on opposite sides of the straight line; first and second FinFETs formed on the substrate based on the first and second fin structures respectively; and a second isolation part between the first and second fin structures and intersecting the first and second fin structures to isolate the first and second fin structures from each other.

Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.

Abstract: An organic EL display device according to an embodiment of the present invention includes: an ITO layer divided and disposed in a region where a pixel opening is formed; a capacitance insulating film disposed on the ITO layer; a lower electrode disposed on the capacitance insulating film; an organic layer disposed on the lower electrode; an upper electrode disposed on the organic layer; and a planarizing member disposed so as to soften a step of a step part of the lower electrode.

Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.

Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.

Abstract: A vertical memory device includes a substrate having a cell array region and a connection region positioned on an exterior of the cell array region. Gate electrode layers are stacked on the cell array region and the connection region of the substrate, forming a stepped structure in the connection region. Channel structures are disposed in the cell array region, extending in a direction perpendicular to an upper surface of the substrate, while passing through the gate electrode layers. Dummy channel structures are disposed in the connection region, extending in the same direction as the channel structures, while passing through the gate electrode layers forming the stepped structure. First semiconductor patterns are disposed below the channel structures, and second semiconductor patterns are disposed below the dummy channel structures. The first and second semiconductor patterns include polycrystalline semiconductor materials.

Abstract: A TFT substrate and a manufacturing method thereof provided, including: depositing a metal thin film and a transparent conductive thin film on TFTs sequentially; coating a photoresist on the transparent conductive thin film, exposing and developing the photoresist via a half-tone mask to obtain a first photoresist layer and a second photoresist layer; etching the transparent conductive thin film and the metal thin film not covered by the first photoresist layer and the second photoresist layer; ashing the first photoresist layer and the second photoresist layer to remove the second photoresist layer; etching the transparent conductive thin film to expose the metal thin film not covered by the first photoresist layer; oxidizing the metal thin film to form a metal oxide thin film as a passivation layer; and stripping off the first photoresist layer to expose the metal thin film and the transparent conductive thin film as the pixel electrode.

Abstract: Described are doped TaN films, as well as methods for providing the doped TaN films. Doping TaN films with Ru, Cu, Co, Mn, Al, Mg, Cr, Nb, Ti and/or V allows for enhanced copper barrier properties of the TaN films. Also described are methods of providing films with a first layer comprising doped TaN and a second layer comprising one or more of Ru and Co, with optional doping of the second layer.

Abstract: Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line region, a cell array structure including memory cells three-dimensionally arranged on the chip region of the substrate, a stack structure disposed on the scribe line region of the substrate and including first layers and second layers that are vertically and alternately stacked, and a plurality of vertical structures extending along a vertical direction that is perpendicular to a top surface of the substrate and penetrating the stack structure.

Abstract: A method includes forming a metal gate structure, wherein the metal gate structure includes a gate dielectric layer and a gate electrode; performing a surface treatment to a top surface of the metal gate structure, wherein the surface treatment converts a top portion of the gate electrode to an oxidation layer; forming a conductive layer above the gate electrode, wherein the forming of the conductive layer includes substituting oxygen in the oxidation layer with a metallic element; and forming a contact feature above the metal gate structure, wherein the contact feature is in direct contact with the conductive layer.

Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

Abstract: A power module includes: a power chip; a control chip controlling the power chip; a power terminal connected to the power chip; a control terminal connected to the control chip; and a package covering the power chip, the control chip, the power terminal, and the control terminal with mold resin, wherein first and second recesses for attaching a fin are respectively provided on side faces facing each other of the package from which neither the power terminal nor the control terminal protrudes, and the first and second recesses are arranged not at positions opposite to each other but alternately.

Abstract: According to an exemplary embodiment of the present disclosure, an organic light emitting element includes: a first electrode; a second electrode overlapping the first electrode; and an emission layer disposed between the first electrode and the second electrode, wherein at least one of the first electrode and the second electrode includes a metal layer including a first material, an oxidation layer including a second material and disposed on two opposing surfaces of the metal layer, and a barrier layer disposed at a surface of the oxidation layer, and the second material has a smaller Gibbs free energy than that of the first material.

Abstract: According to an embodiment of the present invention, self-aligned gate cap, comprises a gate located on a substrate; a gate cap surrounding a side of the gate; a contact region self-aligned to the gate; and a low dielectric constant oxide having a dielectric constant of less than 3.9 located on top of the gate. According to an embodiment of the present invention, a method of forming a self-aligned contact comprises removing at least a portion of an interlayer dielectric layer to expose a top surface of a gate cap located on a substrate; recessing the gate cap to form a recessed area; depositing a low dielectric constant oxide having a dielectric constant of less than 3.9 in the recessed area; and polishing a surface of the low dielectric constant oxide to expose a contact area.

Abstract: A pixel of the display panel includes a first transistor, a second transistor, a first electrode pattern and a second electrode pattern. A first drain of the first transistor is electrically connected with the first electrode pattern. A second drain of the second transistor is electrically connected with the second electrode pattern. The first electrode pattern comprises a first connection portion and a first protrusion. The second electrode pattern comprises a second connection portion and two second protrusions. The second protrusions are respectively connected with two sides of the second connection portion and are extended towards the first connection portion. The first protrusion is connected with the first connection portion and is extended towards the second connection portion and to the location between the second protrusions. The width of the distal end of each of the first protrusion and the second protrusion is smaller.

Abstract: Embodiments of the invention are directed to a method of fabricating a semiconductor device. A non-limiting example of the method including performing first fabrication operations to form nanosheet field effect transistor (FET) devices in a first region of a substrate. The first fabrication operations include forming a first channel nanosheet, forming a second channel nanosheet over the first channel nanosheet, forming a first gate structure around the first channel nanosheet, and forming a second gate structure around the second channel nanosheet, wherein an air gap is between the first gate structure and the second gate structure. A dopant is applied to the first gate structure and the second gate structure, wherein the dopant is configured to enter the air gap and penetrate into the first gate structure and the second gate structure from within the air gap.

Abstract: An integrated circuit is provided having a semiconductor structure, the semiconductor structure including a vertical field-effect transistor; and a diode wherein the vertical field-effect transistor and the diode are co-integrated in the semiconductor structure.

Abstract: A semiconductor structure containing a plurality of stacked vertical field effect transistor (FETs) is provided. After forming a first vertical FET of a first conductivity type at a lower portion of a semiconductor fin, a second vertical FET of a second conductivity type is formed on top of the first vertical FET. The second conductivity type can be opposite to, or the same as, the first conductivity type. A source/drain region of the first vertical FET is electrically connected to a source/drain region of the second vertical FET by a conductive strip structure.

Abstract: A method of forming a memory device that includes forming on a substrate, a first insulation layer, a first conductive layer, a second insulation layer, a second conductive layer, a third insulation layer. First trenches are formed through third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer, leaving side portions of the first conductive layer exposed. A fourth insulation layer is formed at the bottom of the first trenches that extends along the exposed portions of the first conductive layer. The first trenches are filled with conductive material. Second trenches are formed through the third insulation layer, the second conductive layer, the second insulation layer and the first conductive layer. Drain regions are formed in the substrate under the second trenches. A pair of memory cells results, with a single continuous channel region extending between drain regions for the pair of memory cells.