Abstract: A system, method and apparatus for configuring a person detection sensor. The person detection sensor may limit its transmissions in accordance with a pre-configured dwell time. The person detection sensor may receive a new dwell time from a personal communication device. When the new dwell time is received, it is stored in memory and is then used to regulate the number of transmissions of the person detection sensor in accordance with the new dwell time.

Abstract: A method of remotely modifying a basic input/output system (BIOS) configuration setting includes steps of: transmitting, by a remote computer, a modification instruction to a cloud server; transmitting, by the cloud server to a POS system, a new configuration value of the BIOS configuration setting contained in the modification instruction; determining, by an embedded controller of the POS system, whether the new configuration value is identical to an original configuration value of the BIOS configuration setting; and by the embedded controller when a result of the determination is negative, updating the BIOS configuration setting and transmitting a response instruction to the remote computer.

Abstract: A computer program product, system, and computer implemented method for scalable specification and self-governance for autonomous databases, cluster databases, and multi-tenant databases in cloud and on-prem environments. The approach disclosed herein enables management of a consolidated databases using a template-based process that allows for the consolidated databases (CDBs) and pluggable databases (PBDs) to be reconfigured automatically. In some embodiments, the approach instantiates one or more monitoring modules and one or more CDB/PDB configuration managers. These elements can detect relevant changes in the conditions in which CDB instances and open PDBs operate and adjust the configurations thereof in response.

Abstract: Described herein are methods, systems, and computer-readable storage media for seamless offline-online execution of applications. Techniques include receiving at a server a request from a client device for execution of an application and then determining one or more subsets of a logic portion of the application. Technique further include distributing the determined one or more subsets of the logic portion of the application to the client device and receiving a set of operations from the client device and an updated state portion of the application. Technique further include authorizing each operation of the set of operations and finalizing the updated state portion of the application.

Abstract: A method and system to provide timebase synchronization for multiple processors in a multi-processor sensor system, where each processor operates according to a respective reference clock, and where the processors' respective reference clocks are off sync from each other. An example method includes simultaneously injecting a synchronization pulse respectively into the multiple processors. Further, the method includes recording for each processor, according to the processor's respective reference clock, a respective synchronization-pulse timestamp of the simultaneously injected synchronization pulse, comparing the respective synchronization-pulse timestamps recorded for the processors, and, based on the comparing, computing for each processor a respective time offset. Additionally, the method includes using the per-processor computed time offsets as a basis to provide a synchronized timebase across the processors.

Abstract: The method and systems described herein provide for identifying and mitigating undesirable power or voltage fluctuations in regions of a semiconductor device. For example, embodiments include detecting a region, such as an individual processor, of a processor chip is exhibiting a reduced power draw and a resulting localized voltage spike (e.g., a spike that exceeds Vmax) that would accelerate overall device end-of-life (EOL). The described systems respond by activating circuits or current generators located in the given region to draw additional power via a protective current. The protective current lowers the local voltages spikes back to within some pre-specified range (e.g., below a Vmax). The resulting reduction in the time above Vmax in testing reduces the number of devices that will need to be discarded due to Vmax violations as well as increases the expected reliability and lifespan of the device in operation.

Abstract: Methods and apparatuses associated with rebooting a computing device are described. Examples can include receiving at a processing resource of a computing device first signaling associated with boot programs of the computing device and second signaling associated with a boot sequence of the computing device. Examples can include writing from the processing resource to a memory resource data that is based at least in part on the first and the second signaling and writing from the processing resource to the memory resource data representative of activity of the computing device. Examples can include identifying data representative of a boot process for the computing device and rebooting the computing device in a particular sequence including the monitored activity, based at least in part on the data representative of the boot process responsive to a shutdown, restart, or both, of the computing device.

Abstract: A parallel bus phase correction method and a device are provided. The method comprises: correcting a data bus, respectively performing phase correction tests on a clock line; determining a first optimal window of the clock line according to the clock test results; correcting the clock line by using a median value of the first optimal window, respectively performing phase correction tests on the data bus according to the multiple second phase adjustment values, and recording corresponding data test results; determining a second optimal window of the data bus according to the data test results; and performing phase correction on normal data transmission on the basis of the median value of the first optimal window and the median value of the second optimal window. The method achieves phase correction and ensures the correctness and accuracy of data transmission, even if a small clock offset is present.

Abstract: The present disclosure provides systems and methods for managing a temperature of a battery energy storage system (“BESS”). A method may comprise obtaining a charge/discharge schedule for a battery energy storage system (BESS) for a first time period; identifying, from the charge/discharge schedule, a charge or discharge time period of the BESS within the first time period; calculating a beginning time of a temperature control time period in which equipment operates to control a temperature of the BESS to reach a target temperature by a beginning time of the charge or discharge time period; and controlling the equipment operating to control the temperature of the BESS for the temperature control time period such that the temperature of the BESS reaches the target temperature by the beginning time of the charge or discharge time period.

Abstract: A data processing system comprises a pool of reconfigurable data flow resources and a runtime processor. The pool of reconfigurable data flow resources includes arrays of physical configurable units and memory. The runtime processor includes logic to receive a plurality of configuration files for user applications. The configuration files include configurations of virtual data flow resources required to execute the user applications. The runtime processor also includes logic to allocate physical configurable units and memory in the pool of reconfigurable data flow resources to the virtual data flow resources and load the configuration files to the allocated physical configurable units. The runtime processor further includes logic to execute the user applications using the allocated physical configurable units and memory.

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

Abstract: The present disclosure relates to a method for improving the measuring performance of a field device having the following steps: a multiplicity of field devices are configured using a configurations tool; the configuration data and environmental conditions of the field devices at the respective measuring positions are stored in a central data memory as training data, the training data are made available to an adaptive computing program which uses at least one artificial intelligence method; current information relating to the particular application and the environmental conditions at the measuring position of the field device are made available to the adaptive computing program; on the basis of the current information, the adaptive computing program provides the field device to be configured with configuration data on the basis of the multiplicity of training data, which configuration data are matched to the particular application taking into account the environmental conditions.

Abstract: Methods and systems for managing configurable devices are disclosed. A configurable device may be a type of hardware device that may be configured for various purposes. The operation of the configurable device may depend on its configuration. To manage the configurable device, the system may track the configuration of configurable devices and associate the configurations with visual indicators of the configurable devices that are present prior to configuration. The visual indicators may not indicate the configuration of the configurable devices.

Abstract: A node that includes data processing unit (DPU) and a processor, where the processor is configured to perform a method for utilizing a data processing unit (DPU), that includes identifying, by the DPU, a processing entity operatively connected to the DPU, receiving processing entity properties from the processing entity, storing the processing entity properties in a processing entity catalog, generating a virtual combined memory space in the processing entity catalog, and providing access to the processing entity catalog to a BIOS.

Abstract: A server is provided. The server includes a Basic Input/Output System (BIOS) memory, a storage device, and a processing unit. The BIOS memory stores a BIOS code, and the BIOS code provides a BIOS setup menu and a saving option in the BIOS setup menu for setting information of a plurality of BIOS setup items. The processing unit is coupled to the BIOS memory and the storage device. The processing unit executes the BIOS code during a power-on self-test (POST) process of the server. When executing the saving option, the processing unit stores the setting information of the plurality of BIOS setup items into the BIOS memory and the storage device, and the processing unit also stores a designated file name into the storage device, the designated file name corresponding to the setting information of the plurality of BIOS setup items that is stored into the storage device.

Abstract: The present document relates to a method of synchronizing devices, wherein each device operates in sync with an internal clock signal which is periodic to thereby define time cycles, at least one of the internal clock signals being periodic at a first frequency. The devices are mutually synchronized via a party line. The method comprises providing a system clock signal periodic at a second frequency smaller than the first frequency defining sequential system clock cycles; and synchronizing the internal clock signal with the system clock signal. At least one device triggers, in sync with the system clock signal, a system synchronization event comprising changing a signal status of a common party line signal on the party line and monitoring the common party line signal. The changing and monitoring are performed in sync with the system clock signal.

Abstract: An operation support apparatus (100) includes a storage unit (110) configured to store time-series data (111), and operation information (112), a specification unit (120) configured to specify a plurality of change points in a change trend of the states from the time-series data (111), and specify each of a plurality of time windows as one of a plurality of operating modes in the target system, and an operation-set generation unit (130) configured to extract, for each of the plurality of time windows, a set of operations performed at a time included in that time window from the operation information (112), generate an operating-mode operation set (113) in which the operating modes corresponding to the respective time windows are associated with the extracted set of operations, and stores the generated operating-mode operation set (113) in the storage unit (110).

Abstract: A method for synchronizing clocks of at least two devices in a distributed network of a vehicle, comprising: establishing unencrypted communication between the at least two devices to determine a temporal difference between the clocks of the two devices, exchanging messages between the at least two devices via the unencrypted communication, ascertaining a temporal difference between the clocks of the at least two devices using the messages, establishing encrypted communication between the at least two devices to authenticate the exchange of messages, authenticating the messages that were used to ascertain the temporal difference, using the ascertained temporal difference, when the authentication of exchanged messages has been completed successfully.

Abstract: The present disclosure generally relates to reducing boot latency of memory devices in a dual boot system. The boot code is loaded to the data storage device controller in a flexible manner by being able to receive chunks of the boot code from two separate locations, the host memory buffer (HMB) and the memory device, which may be a NAND device. Part of the boot code may be received from the HMB and another part of the boot code may be received from the memory device. If either the HMB or the memory device can deliver the chunks faster than the other, then the controller can receive the chunks from the faster location and periodically confirm the speed of delivery to ensure the boot code latency is optimized.

Abstract: A method of remotely modifying a basic input/output system (BIOS) configuration setting includes steps of: transmitting, by a remote computer, a modification instruction to a cloud server; transmitting, by the cloud server to a POS system, a new configuration value of the BIOS configuration setting contained in the modification instruction; determining, by an embedded controller of the POS system, whether the new configuration value is identical to an original configuration value of the BIOS configuration setting; and by the embedded controller when a result of the determination is negative, updating the BIOS configuration setting and transmitting a response instruction to the remote computer.