Abstract: A chipset (platform)-independent method and apparatus for compressing and decompressing a system ROM of a computer (e.g., BIOS, setup program, and one or more option ROMs) are disclosed. The setup program, option ROM, and part of the BIOS are compressed using a lossless compression algorithm. A non-compressible portion of the BIOS includes a decompression algorithm and a shadow RAM block table of chipset-specific registers and bit patterns to write-enable and read-enable shadow RAM (RAM that is mapped to the ROM address space). The compressed data is stored in a compressed data block format with the associated location in memory to decompress the compressed data. Thus, the data can be decompressed anywhere in memory of a target computer. For example, the BIOS is decompressed to shadow RAM and the setup program is decompressed to conventional memory. During the BIOS Power-On Self-Test (POST) process, the compressed system ROM is copied to conventional memory, and the decompression program is executed.

Abstract: A method for loading a software application for use at a client node (24, 30) of a network (12, 14) includes activating a program loader system (48) at the client node (24, 30). A user-specific software application setup file (56) is then transmitted from a file server (22, 28) to the client node (24, 30).

Abstract: In a computer network, a master computer has an operating system (OS) management table for mapping unique addresses of the network computers to respective versions of an operating system and a status table for mapping the unique addresses to respective busy/idle states of the computers and to respective queues. A list of the OS versions is retrieved from the management table to allow user at a source computer to select one of the versions, and a request is sent to the master computer. In response, the master computer makes a search through the management table for remote computers in which the operating system of the selected version is installed and makes a search through the status table to determine their busy/idle states and to detect one of their queues having shortest length if all of the remote computers are busy.

Abstract: An integrated circuit allows a user or system designer to program the length of a transaction cycle by programming the lengths of the setup time period, the command time period and the recovery time period, individually. An eight-bit register is used to store a two-bit prescaler value and a six-bit count value for each of the setup, command and recovery time periods. The value represented by the prescaler is then multiplied by the count value and the resulting value is input to a timer which counts down from the resulting value, signalling to a state machine when it has reached zero. A four-state state machine sends the command to begin each transaction cycle and each setup, command and recovery time period within each transaction cycle. The state machine is notified by the timer when the time period has elapsed for each of the three states so that it can send the signal to begin the next state.

Abstract: An improved operating system for a computer provides support for specific hardware components. The operating system is loaded by first loading a base portion which initializes the operating system and determines the particular type of hardware components present. Then, appropriate software components are loaded that are specifically associated with the hardware components. The hardware components can be detected by leaving a trace in the memory device that is associated with the software component and later retrieving the trace, or by testing the computer for the hardware component. The hardware component may be a bus architecture selected from a group of bus architectures, and bus-independent interfaces are defined which are mapped to addresses in the kernel. Alternatively, the software component can include a PAL which contains specific instructions for communicating with the hardware component. The PAL is constructed from a plurality of files each associated with the hardware component.

Abstract: A method of scheduling tasks subject to timing and succession constraints essentially comprises grouping the tasks in layers according to succession constraints and scheduling the tasks layer by layer in increasing layer order up to the last layer, if possible, and then deciding that the resulting scheduling succeeds. If the scheduling achieved in a layer other than the first layer does not satisfy one or more constraints applying to a task belonging to the current layer, the method reschedules a layer containing a predecessor task corresponding to an unsatisfied constraint, schedules or reschedules all the other layers higher than the layer of the predecessor task, up to the last layer, if possible, and then decides that the resulting scheduling succeeds. Applications include scheduling of transmission of information on an industrial data bus.

Abstract: A job re-execution system includes a status output controller for outputting a process status listing of each job, to an output unit. The processes to be re-executed are selected with an input unit. A process controller controls a processor to execute the processes. The processes to be re-executed are also selected by a re-execution controller.

Abstract: The invention provides the ability to interactively select and configure a product among a set of related products based on availability and compatibility of features and options. It does not impose an order in the selection of products, features or options; only valid selections can be made at any time. To create an electronic representation of the product information to achieve the above goal, the invention provides a framework for defining a systems by defining the components of the system using elements contained in a parts catalog and defining relationships between the components of a system. A configuration system validates a configuration using the system definition, the current state of the configuration and user input.

Abstract: A multi-boot apparatus allows a portable computer to boot from a predetermined list of bootable data storage devices, even if the data storage devices have been relocated during operation. The computer system has a hard disk bay and multi-bay for accepting one or more data storage devices and/or battery packs. During initialization, the invention retrieves a previously entered IPL sequence from a configuration setup table stored in the nonvolatile RAM of the portable computer. Next, the invention queries each bay and determines the device connected to each bay, including the data storage device and the battery pack, if one is present. The invention then determines if a remapping of the data storage drives is necessary to ensure that the device at the beginning of the IPL order is the first drive in the BIOS boot sequence. If so, the invention remaps the drives such that the device is at the first drive in the BIOS boot sequence.

Abstract: The dbX persistent programming language model solves the problem of seamlessly providing an unfragmented, persistible, complex object heap space that extends beyond virtual memory to a program in a host programming language X. It does so without rewriting a compiler for X and without operating system or hardware dependencies. It uses a memory pointer as a pointer to a persistible object, with the lvalue of the pointer providing a hook to the OID of the object. The lvalues of pointers to persistible objects, their associated OIDs and other information about persistible objects are maintained in a global data structure. Unresolved pointers to persistible objects point to an unusable area of memory, and dereferencing them triggers object faulting. A keyword and an overloaded allocation operator are used to identify statically and dynamically allocated pieces of memory respectively as persistible.

Abstract: A computer system is provided for storing CMOS configuration information in FLASH and for retrieving a copy of the CMOS configuration information stored in FLASH into a CMOS RAM memory. The computer system includes a processor, a computer readable CMOS RAM memory device coupled to the processor, the CMOS RAM devices having system configuration information programmed therein. The computer system further includes a computer readable RAM memory device coupled to the processor, a computer readable non-volatile memory device coupled to the processor, the non-volatile memory having a first block of memory including CMOS RAM configuration information programmed therein.

Abstract: A computer system having a processor, a microcontroller, a flash ROM is provided with an address remapper for handling warm-boot events, and an arbiter for selectively assigning the ownership of the flash ROM to either the microprocessor or the microcontroller. The arbiter assigns the flash ROM initially to the microcontroller when power is initially provided to the system. After the flash ROM boots up and checks the integrity of the flash ROM and updates the content of the flash ROM with valid firmware if necessary, the microcontroller releases the flash ROM to the microprocessor to enable the computer system to proceed with the normal boot-up process. In this process, various system self tests are performed. Next, the microprocessor copies or shadows one or more portions of the flash ROM BIOS into a main memory array. After the shadow operation, the processor sets a remap bit to indicate that the ROM BIOS content has been copied into the main memory array.

Abstract: The present invention provides a method in a computer system of integrating a compression system with an operating system. The computer system preferably comprises at least a memory device and one storage device. A user-supplied device driver is provided for storage devices that are not supported by the computer system to enable the computer system to communicate with the storage devices. In response to initialization of the computer system, the operating/compression system is loaded into the memory device and begins executing before any user-supplied device drivers are loaded into the memory device. Any compressed volume files located on the computer system are assigned drive letters at this time. When the user-supplied device drivers are loaded into the memory device, drive letters are assigned to the various storage devices. A drive letter conflict resolution scheme is provided to resolve conflicts that occur when the operating system attempts to assign a drive letter.

Abstract: An apparatus and method for implementation in a computing system (5) which allows the transfer of control from one process (10) to another process (40). The input/output supervisor (20) and a newly provided control mechanism (50) are used to switch control. Transfer of data between the two processes is carried out using a data pool (75). This data pool (75) is accessible to both processes (10, 40) through the control mechanism (50).

Abstract: An apparatus and method for downloading firmware upgrades to a targeted remote field configurable embedded computer system over a computer network. The targeted device need not be disconnected from the network and requires no human intervention at the remote site. The entire firmware, including the downloading mechanism, can be updated in an efficient manner.

Abstract: A method and system for swapping blocks of data between a main memory area and a secondary storage area of a computer system that uses absolute addresses as its native addressing format. A series of linked information structures is maintained in the main memory area of the computer system. Each information structure allocates storage for a near return address pointer, a previous information structure pointer, a reference number and an offset. A first and second data block are swapped into the main memory area of the computer system. When the first data block transfers control to the second data block, a memory location indicating an absolute address for this point of transfer is stored in an information structure associated with the first data block. Prior to swapping the first data block out of the main memory area, the absolute address is resolved into a reference number and an offset. This resolved address is then stored in an information structure associated with the first data block.

Abstract: Described herein is a system and method for enabling an application to pass a structure containing a pointer member to an external entity, wherein the application represents a computer program executing in a computer system, and the computer program is written in a computer programming language that does not support pointers. The application declares a variable V, a structure type having a member P, and a variable M of the structure type. The application invokes a function written in a computer programming language that supports pointers. A reference to the variable V is passed to the function. The function, when executed, obtains and returns an address of the variable V. The application sets the member P in the variable M equal to the address of the variable V. The application then passes the variable M to an external entity. In this manner, the present invention enables a structure having a pointer embedded therein to be passed to the external entity.

Abstract: An essential utility routine accesses a protected computer system component by making a call to a coprocessor that performs a desired function to avoid security measures imposed by an operating system. Various suitable coprocessors include an additional coprocessor connected to a host processor running the operating system imposing the security measures such as a coprocessor on a add-in card to a computer system, a microcontroller, or a system management mode (SMM) program running on the host processor. The essential utility operates on a computer system having a processor operating under an operating system and a storage. The operating system includes software which limits access to the storage. The utility includes a coprocessor, a software interface and a utility routine. The coprocessor is connected to the storage and operative independent of the operating system for accessing the storage.

Abstract: A debugger for use in connection with a parallel computer including a plurality of processing nodes. The debugger enables the operator to establish a processing node set in response to certain criteria, such as the respective identifications of the processing node and their prior processing under the debugger. The debugger, in response to a processing node set establishment command from the operator, enables each processing node to establish and condition a set membership flag in response to the operator-supplied set membership criteria. The debugger is then responsive to a debugging command from the operator to enable the processing nodes to use their respective set membership flags to condition their execution of the debugging command.

Abstract: A system and method for managing the maintenance of computer software is provided. The invention receives a software maintenance module. The invention verifies the validity of the software maintenance module. The invention builds a maintenance job for the software maintenance module. The invention determines whether the software maintenance module requires test, and submits the module to test if required. The invention evaluates the installation and/or test results of a software maintenance module. The invention sends the software maintenance module to end users. The invention coordinates the exchange of information between software developers, system managers, and end users. The invention performs oversight functions on a periodic basis. The invention provides a user interface for manual control of automatic functions.