Abstract: A method for downloading software includes transmitting only that portion of the program which is to be updated or otherwise changed. In a preferred aspect, a key is also transmitted which must match a key last stored in EEPROM, to permit the download to be effected.

Abstract: A method, apparatus, and article of manufacture for pre-initializing, maintaining, and terminating a persistent language execution environment. The pre-initialization function allows the specification of a termination exit routine that is invoked on any attempted termination of an object program within the language execution environment, regardless of whether the attempted termination is initiated voluntarily or involuntarily.

Abstract: A method and apparatus for performing load operations in a computer system. The present invention includes a method and apparatus for dispatching the load operation to be executed. The present invention halts the execution of the load operation when a dependency exists between the load operation and another memory operation currently pending in the system. When the dependency no longer exists, the present invention redispatches the load operation so that it completes.

Abstract: A method for displaying panels from an ISPF panel library using an XEDIT macro written with the REXX language under a virtual machine operating system is disclosed. Interactive System Productivity Facility capabilities are imparted to a non-ISPF operating system. The method allows a software application to easily except an ISPF panel library using standard components eliminating the need for a separate ISPF program product. Macro stemmed variables are utilized to construct within a REXX programming language so that the stemmed variable can be traversed using a counter for the `Y` component only.

Abstract: A computer method and system for passing a pointer to an interface from a server process to a client process. In a preferred embodiment, the server process instantiates an object that has multiple interfaces. The server process identifies an interface to pass to the client process and creates a stub object for receiving a request to invoke a function member of the interface and for invoking the requested function member upon receiving the request. The server process then sends an identifier of the stub to the client process. When the client process receives the identifier of the stub, it instantiates a proxy object for receiving requests to invoke a function member of the interface and for sending the request to the identified stub. The client process can then invoke the function members of the interface by invoking function members of the proxy object. The proxy object sends a request to the identified stub. The identified stub then invokes the corresponding function member of the interface.

Abstract: A computer system and a computer-implemented method are described which may be used in a distributed client/server computing environment to convert an exception identifier received by a host computing system from a remote device to a more readable message string that corresponds to the exception identifier. The exception identifier is arranged to uniquely identify the exception. Initially, the exception identifier is used to help identify an exception tag that includes a domain name and a message identifier. The message string that corresponds to the exception identifier is then found based at least in part upon the domain name and the message identifier. More specifically, the domain name is used to identify an exception message file that corresponds to the remotely located device. The message identifier is then used to locate a message string within the exception message file that corresponds to the exception indicated by the exception identifier.

Abstract: An interactive, information logging and processing tool that provides information regarding a process's data structure utilization to reduce the working set of a process's dynamically allocated memory. The actual working set (AWS) determinant determines which portions of the dynamically-allocated pages, referred to as the process's virtual memory (VM) working set (VWS) are actually used. It then determines the actual working set of a dynamically allocated memory for a given benchmark. The basic approach of the AWS determinator is to observe which data structures cause page faults when the targeted process is severely thrashing. AWS determinator includes a data logger and a data analyzer.

Abstract: An apparatus for synchronously detecting phase relationships between a high-frequency clock and a low-frequency clock that are substantially synchronous. The low-frequency clock is frequency divided-by-two to generate a LFdiv2 signal. The LFdiv2 signal is synchronously delayed by one phase of the high-frequency clock to generate a dLFdiv2 signal. The LFdiv2 and dLFdiv2 signals are compared using an XOR gate to generate a PH1 signal. A rising-edge of the PH1 signal indicates that a rising-edge of the high-frequency clock corresponds to a rising-edge of the low-frequency clock. This phase information allows enhanced communication between state machines or buses that are operating at different frequencies.

Abstract: It is an object of the present invention to provide a state-transition-model-based programming system where the program data structure is simple and compact. To achieve this object, one or more specifications comprising a program are entered from the input unit (11) and specification input section (12) in the from of state transition models. The specification storage means (21) stores the specifications. The specification execution section (32) executes the specifications. When one of the beginning conditions is satisfied, the priority processing section (33) changes the specification to the next specification corresponding to the beginning condition. The change processing section (34) determines the beginning state of the next specification according to the correspondence stored in the state map storage means.

Abstract: A method and system for tracking, and resolving links to, objects that derive from a common object creation is provided. In a system, the system creates a source object. The system then generates a lineage identifier to identify the creation of the source object. Then the system associates the lineage identifier with the source object. At a later time, the system copies the created object to a copy object. When the source object is copied to a copy object, the system associates the lineage identifier associated with the source object with the copy object. In this way, the lineage identifier associated with the copy object indicates that the copy object derives from the creation of the source object.The system links a client object to a source object by storing a link containing the source object's lineage identifier in the client object. A link also contains information for distinguishing the source object from other objects having the same lineage identifier.

Abstract: A method and apparatus for performing operations with a processor in a computer system. Load operations are performed by use of a dispatch pipeline and a memory execution pipeline. The dispatch pipeline dispatches the load operation for execution by the processor, while the memory execution pipeline controls the execution of the load operation to memory. The present invention reduces the latency involved in executing a load operation by coupling the execution of the two pipelines during execution of the load operation.

Abstract: A computer with a pipelined processor and code breakpoints for performing software debug operations includes prefetch and decode stages, debug address registers for storing code breakpoints representing addresses of preselected instructions, and two digital comparators. During the instruction prefetch phase of operation, the first comparator compares the 29 most significant bits ?31:3! of the 32-bit prefetch instruction address against the code breakpoints stored in the debug address registers and produces a 1-bit signal indicating whether such comparison results in a positive match. Subsequently, during the decode phase of operation, the second comparator compares the three least significant bits ?2:0! of the 32-bit prefetch instruction address and produces a 1-bit signal indicating whether such comparison results in a positive match.

Abstract: A method and apparatus are provided that significantly reduces the inconvenience of placing a computer system in a useful state. The invention quickly boots the system without preinstalling the operating system and allows installation of the operating system to occur without usurping the computer's resources from a user. A full version of the operating system is made accessible to the user by a boot device having sufficient capacity to hold the full operating system. A local media of the computer system is formatted so that the operating system may perform memory management functions, such as paging and swapping, if necessary. Consequently, the system is usable without requiring preinstallation of the operating system. The files relating to the operating system may be transferred from a boot device to a local media at a more convenient time, or performed as a concurrent or background process.

Abstract: The present invention provides a method and apparatus for dynamically modifying the priority of access to a bus, where the bus has control and arbitration functions distributed among the devices coupled to the bus, with each device having a fixed priority level. Access to the bus by particular devices is selectively inhibited, preventing them from asserting their fixed priority level. In a preferred embodiment, the present invention provides control over the reselection of a SCSI bus by a plurality of SCSI devices coupled to the bus by providing a pseudo busy signal to SCSI devices from which reselection is not desired. In this fashion, an initiator may issue a plurality of commands to the SCSI devices and control the order in which the devices will be serviced when ready. A plurality of pseudo busy circuits are provided, with one coupled to each device on the bus. Each pseudo busy circuit is controlled by a control signal from the initiator.

Abstract: A data communications system memory interface circuit (32) is provided which operates within an adapter circuit (10). Adapter circuit (10) comprises a communications processor (28), a system interface (30) and a protocol handler (20) coupled together by an adapter bus (26). Communications processor (28) accesses an external memory (38) through a memory interface (32). Memory interface (32) comprises a map register circuit (36) which comprises a number of map registers (44 through 56). The map registers (44 through 56) each are operable to store a portion of a twenty bit address which may be selected by a multiplexer (42) responsive to control signals generated by a control logic circuit (40). The address portion stored in the map registers (44 through 56) are added to a remaining portion of an address to form a complete twenty bit remapped address.

Abstract: An improved method of installing device drivers or utility programs on a data processing system is disclosed. Provided are a plurality of command specifications relating to installation operations for the device drivers or the utility programs. Installation programs on media introduced to an auxiliary memory units are identified, wherein the program include statement instances invoking selected command specifications. A list of the identified installation programs is built and the selected command specifications invoked by the statement instances called. Executing the command specification returns interpretable code for the installation programs. Upon running the installation program the interpretable code is interpreted.

Abstract: A system for managing software development in a distributed development environment, divided into personal layers (P) consisting of logical hierarchies for performing work for development and management of individual resources on an individual level, group layers (G) consisting of logical hierarchies for performing work for development and management of subsystem resources by groups receiving the individual resources developed at the personal layers (P), and a master layer (M) consisting of a logical hierarchy for performing work for development and management of integrated project system resources by a project receiving the subsystem resources developed at the group layers (G), which ensures cooperation among the layers and integrates the plurality of resources prepared at a plurality of distributed bases into a single software system, thereby enabling reduction of delays in software development and improvement in the software quality.

Abstract: The cold boot data backup apparatus maintains an index of all data file activity on a computer system and stores copies of data files in a manner to enable a user to recreate the state of the computer system at any selected point in time. This apparatus automatically formats the computer system memory in response to a failure thereof and automatically restores the operating system, all application programs and every data file that is selected by the user to be monitored and preserved by this apparatus.

Abstract: A method for analyzing and optimizing programs that define and use aggregate data structures. A program to be analyzed and optimized is inspected to find definitions and uses of lvalues, which are regions of memory. The lvalues may be denoted by program variables, pointer expressions, or components of aggregate lvalues. A data-flow solver determines where definitions of lvalues reach uses. A set of "least general unifiers" are computed for the definitions and uses. A replacement variable is created for each least general unifier that is determined to be replaceable. Each reference to an lvalue that corresponds to a replaceable least general unifier is replaced by a reference to the corresponding replacement variable or a component thereof. The method is applicable even in the presence of potential aliasing.

Abstract: A parallel computer includes a plurality of processor elements (1-1 to 1-n) connected by a network (2); each processor element includes a local memory (6) for holding a program and related data, a processor (3) for performing an instruction in said program, a circuit (5) for transferring data to other processor elements, and a circuit (4) for receiving data sent from another processor element; a memory area (92,8) includes of a plurality of reception data areas for temporarily storing data received by said receiving circuit, and memory (92,8) constructed of a plurality of tag areas, provided for each reception data area, for storing a data tag indicating validity of data in the corresponding reception data area; a transmitting circuit (5) for transmitting data with an attached data identifier predetermined by said data; a circuit for writing the data into one of the plurality of reception data areas in response to data received from the network, and writing valid data tag into one of said plurality of recepti