Abstract: In a music synthesis system, a scanning apparatus repeatedly scans a physical attribute of a vibrating object at a sequence of points of the vibrating object so as to repeatedly generate corresponding sequences of values. The music synthesis system generates an audio frequency waveform whose shape corresponds to the sequences of values. The vibrating object may be a physical object or a simulated object. The system may include a sensor for receiving user input, and means for mapping the user input into a stimulus signal that is applied to the vibrating object. In a preferred embodiment, the object vibrates and is manipulated by the user at haptic frequencies (0 to 15 hertz), while the sequences of scanned values are cyclically read at an audio frequencies so as to generate an audio frequency waveform whose timbre varies at the haptic frequencies associated with the object's vibration.

Abstract: A method for providing producibility information to a user during a design process includes providing process capability models with integrated coaching information and providing a producibility evaluation worksheet having at least one input and at least one output, the input being selectable to represent a specific design. The worksheet is initialized with a relevant process capability model that is used to determine a producibility measure indicating an effect of the input on the output. The producibility measure is then displayed to the user.

Abstract: The system and method of the present invention is embodied in a multi-state on-chip logic analyzer that is preferably integrated into a VLSI circuit. In general, the logic analyzer is preferably coupled to a multilevel trace array for storing event trace data generated by the logic analyzer. Input and output logic coupled to both the trace array and the logic analyzer allows reading or writing from or to the trace array, and programming of trigger and condition criteria for transitioning states within the logic analyzer. The logic analyzer has the capability match one or more programmable trigger events to satisfy one or more programmable conditions. Further, the logic analyzer preferably has the capability to initialize programmable conditions in desired states, and to store event trace data in an on-chip array for trace data reconstruction and analysis.

Abstract: Apparata and methods for rapid design of objects/shapes in Computer-Aided Design (CAD) tools and in Virtual Reality (VR) environments are described. The underlying geometric representation of the objects within the design tool is optimized so that design activities such as modeling, editing, rendering, etc. can be processed extremely rapidly, thereby enhancing the response time of the design tool. The representation is preferably provided in two parts, which may be referred to as a “design intent model” and a “shape model”. The design intent model is a higher-level representation wherein elements are arranged in hierarchical parent-child relationships which record the elements' assembly sequence. The shape model is a lower-level representation storing more detailed information about the elements and their relationships.

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of ‘cascade’ connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract: A computer implemented method which does not require a stored dictionary for correcting spelling errors in a sequence of words comprises storing a plurality of spelling rules defined as regular expressions for matching a potentially illegal n-gram which may comprise less than all letters in the word and for replacing an illegal n-gram with a legal n-gram to return a corrected word, submitting a word from said sequence of words to the spelling rules and replacing a word in the string of words with a corrected word.

Abstract: A user uses part data forming means 101 and module data forming means 102 to input the actual dimension, physical constants and mesh dividing number for fundamental shapes which are registered in advance, thereby forming parts, and then indicates the relative position between the parts to form the entire shape of an assembly of plural parts without paying attention to coincidence or non-coincidence of nodal points. Data converting means 104 divides the shape of each part thus assembled according to the indicated mesh divisional number to generate element data and nodal point data. Further, it generates a constraint equation for connecting nodal points which are non-connected between neighboring parts, and forms an analysis model 401. A finite element method analyzer 105 uses approximate calculation means 106 to approximate a non-connected nodal point displacement from a nodal point displacement of neighboring structural elements on the basis of the constraint equation.

Abstract: An emulation device is provided that has a processor core that is a programmable digital signal processor (DSP). Several blocks of memory within the emulation device can be configured to emulate blocks of memory on a target processor system. Each block of memory responds to three different memory buses and can receive up the three simultaneous memory requests. Arbitration circuitry selects the highest priority memory request for service on each cycle. Each memory block is configured to respond to a block of addresses beginning at a selected starting address. Two blocks of memory can be linked to form a single merged block of memory in which both arbitration circuits operate in lock step by masking a most significant address bit of the block of address selected for the memory block.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: The present invention includes simulation system devices and methods. The invention can be used to collect information describing a desired data exchange between simulated devices and can assist in the generation of simulation model control programs that implement the desired data exchange. The disclosed methods feature generating simulation control code by interacting with a user to receive an address constraint and by generating a collection of data transfer instructions. Each data transfer instruction includes a data transfer address selected from a collection of addresses. The disclosed systems feature a simplified simulation data entry system including means for receiving address constraint information delimiting a collection of data transfer address values and means for generating a collection of simulation data transfer instructions. Each data transfer instruction may include an address selected from the collection of data transfer address values.

Abstract: A method and structure for analyzing the effect of electrical noise in an integrated circuit fabricated in a silicon-on-insulator (“SOI”) technology. The present invention uses a static noise analysis to evaluate an integrated circuit's response to electrical noise, taking into account hysteresis effect and parasitic bipolar current voltage, both of which are unique to integrated circuits fabricated in a SOI technology process. The present invention also includes a computer, computer storage device, computer program and software incorporating the method steps and simulating the testing and analysis of the circuit under test.

Abstract: An electronic device includes an operation processing unit, a main storage unit, a program storing ROM for storing a plurality of divided program codes and for storing loading program codes for loading the program codes to the main storage unit, an information table storing ROM for storing an information table having a description of information about the program codes to be loaded from the program storing ROM to the main storage unit, and a map management element having a description of virtual addresses in the main storage unit at which the program codes stored in the program storage element are mapped. As a result of this construction, only those program codes requiring quick response are loaded without loading all the program codes to the main storage unit and executed promptly, and thus the system activation time can be reduced.

Abstract: The present invention provides a method and apparatus for evaluating nodes in an integrated circuit to determine whether or not networks containing the nodes meet certain design criteria. The method and apparatus of the present invention are embodied in a rules checking system which evaluates the nodes in the integrated circuit to determine whether or not the networks in the integrated circuit comply with the design rules. Compliance with any particular rule is verified by performing one or more checks on the particular node being evaluated. Some checks require less time to perform than others. In some cases, the result of a single check can provide a determination as to whether or not the network containing the node being evaluated complies with the rule associated with the particular check. Furthermore, some checks are less expensive in terms of the amount of time required to perform them than other checks.

Abstract: A computer-implemented system analyzes user-inputted hypothetical situations of an electrical distribution network design and automatically interprets, based on user input, a need to conduct analyses that improve reliability of the electrical distribution network. The computer-implemented system includes a storage device configured to store different configurations of the distribution network, data corresponding to elements of the distribution network, and a set of engineering analysis modules. The computer-implemented system includes a controller configured to display and use a graphical user interface (GUI) to prompt a user to answer one or more questions about the distribution network. The controller is configured to receive answers and data from the user and retrieve data corresponding to elements of the distribution network. Then, the controller automatically selects and runs one or more of the engineering analysis modules based on the received answers.

Abstract: An apparatus is provided for diagnosing the state of health of a vehicle and for providing the operator of the vehicle with a substantially real-time indication of the efficiency of the vehicle in performing an assigned task with respect to a predetermined goal. A processor on-board the vehicle monitors sensors that provide information regarding the state of health of the vehicle and the amount of work the vehicle has done. In response to anomalies in the data from the sensors, the processor records information that describes events leading up to the occurrence of the anomaly for later analysis that can be used to diagnose the cause of the anomaly. The sensors are also used to prompt the operator of the vehicle to operate the vehicle at optimum efficiency.

Abstract: An apparatus and method for determining register dependency in multiple architecture system. The system includes a microprocessor emulating an emulated instruction set using a native instruction set where the microprocessor contains at least one register. An execution engine provides the native instructions where each native instruction contains at least one register identifier. Flags are provided to each native instruction where each flag indicates whether a register identifier is valid. A bundler checks for dependency among the valid register identifiers in the native instructions.

Abstract: The present invention is generally directed to a system and method for identifying nodes in a circuit design that are susceptible to floating. In accordance with one aspect of the invention, a method identifies nodes susceptible to floating by first detecting a node that is an output of a pass gate. The method then evaluates the circuit structure surrounding the node to ensure that the surrounding circuit structure is not one of several permissible structures. In this regard, the method ensures that the node is not an output node of a static gate. It also determines that the node is not an output of a multiplexer. If further verifies that the node is not an output of a pass gate that is always on. In addition, the method determines that the node drives a FET gate. In accordance with another aspect a computer readable storage medium, containing program code for evaluating a netlist, may be provided to detect a node that is susceptible to floating comprising.

Abstract: A method for simulating an integrated circuit includes dividing the integrated circuit into a plurality of independent subcircuits using a digital simulator, electrically simulating each of the independent subcircuits for a simulation result, and linking together the simulation results. By splitting the simulation of the integrated circuit into a plurality of simulations of smaller independent subcircuits, the electrical simulation is faster and can be performed in parallel since each subcircuit is independent.

Abstract: A method of generating a display, or representation, of a simulation model within a graphical user interface (GUI) is described. The simulation model includes a number of objects, which may include state, function, link and modifier objects. The method commences with the display of node representations for at least first and second objects. Thereafter, a link representation, which represents an underlying link object, is selected from a predefined set of link representations to represent a desired relationship condition between the first and second objects. Each link representation of the set is associated with a distinct relationship condition. Each relationship condition may further be defined in terms of an underlying equation. Thereafter, the selected link representation is shown to extend between the respective node representations representing the first and second objects.

Abstract: A method and system for locating possible error or fault sites in a circuit or system. A set of nodes are chosen, using error models in some embodiments. By applying X values to the set of nodes in conjunction with three valued logic simulation output responses between the circuit and the specification are determined. Based on the comparison of the output responses between the circuit and the specification, an error probability can be assigned to the set of nodes. A ranked set of nodes is thereby produced with the highest ranked set of nodes being the most likely error or fault site. Furthermore, by determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes in conjunction with test vectors and output responses determined in the specification, an error probability can also be assigned to the set of nodes. Use of symbolic logic variables can assist in determining the relationship of the inputs to the set of nodes to the outputs of the set of nodes.