Abstract: A hardware emulator chip contains an array of cells and a programmable interconnection array. Each cell performs only a single logic function, which is configurable. The chips run asynchronously to one another, and within each chip cells are enabled by a sequential wave signal, which enables successive logical rows of cells. Within the chip, it is possible to connect any arbitrary cell output to any arbitrary cell input. Preferably, a set of off-chip connections is made possible by time-multiplexing the output of each subset to the wave signal. In one embodiment, full interconnection of cells within a chip is provided by providing a time-multiplexed programmable array of interconnect switches, the setting of each switch changing with each successive wave. In a second embodiment, full interconnection of cells within a chip is provided by providing a programmable array of interconnect switches.

Abstract: DC margin of a latch of a circuit under design is determined by performing three simulations. A simulation is performed to find the trip voltage of the forwarding inverter of the latch. A second simulation is performed to find the one margin of the latch. Lastly, a third simulation is performed to find the zero margin of the latch. During each of the simulations to find the one margin and the zero margin, the worst case input signal path from the various driver circuit elements and signal paths within the circuit under design is determined analytically by accumulating weighted resistance of each of the circuit elements along the signal paths. The weights assigned to the circuit elements are empirically determined based on the topology configuration of each of the circuit elements, e.g., the type circuit element, the signal being passed through the circuit element and whether a threshold voltage drop occurs between the drive circuit element and the pass circuit element.

Abstract: Disclosed herein is an improved logic module used for logic emulation along with an enhanced logic emulation board subject to logic verification. The logic module has a plurality of programmable LSIs capable of programming logic and a plurality of switching LSIs capable of programming connections, the LSIs being mounted on one or both sides of a board. Peripheral portions of the board carry connectors for electrical connection to the outside. There are two types of data lines: those directly coupling the connectors to the programmable LSIs, and those linking the connectors to the programmable LSIs via the switching LSIs. The programmable and switching LSIs constitute a crossbar connection arrangement. The logic emulation board has connectors for connection to a logic emulation module, and lands for supporting LSIs targeted for development. Pins of the connectors and the lands are interconnected on a one-to-one basis.

Abstract: A methodology for process modeling and control and the software system implementation of this methodology, which includes a rigorous, nonlinear process simulation model, the generation of appropriate linear models derived from the rigorous model, and an adaptive, linear model predictive controller (MPC) that utilizes the derived linear models. A state space, multivariable, model predictive controller (MPC) is the preferred choice for the MPC since the nonlinear simulation model is analytically translated into a set of linear state equations and thus simplifies the translation of the linearized simulation equations to the modeling format required by the controller. Various other MPC modeling forms such as transfer functions, impulse response coefficients, and step response coefficients may also be used. The methodology is very general in that any model predictive controller using one of the above modeling forms can be used as the controller.

Abstract: A method is provided for scaling up permeabilities associated with a fine-scale grid of cells representative of a porous medium to permeabilities associated with an unstructured coarse-scale grid of cells representative of the porous medium. An areally unstructured, Voronoi, computational grid is generated using the coarse-scale grid as the genesis of the computational grid. The computational grid is then populated with permeabilities associated with the fine-scale grid. Flow equations are developed for the computational grid, the flow equations are solved, and inter-node fluxes and pressure gradients are then computed for the computational grid. These inter-node fluxes and pressure gradients are used to calculate inter-node average fluxes and average pressure gradients associated with the coarse-scale grid. The inter-node average fluxes and average pressure gradients associated with the coarse grid are then used to calculate upscaled permeabilities associated with the coarse-scale grid.

Abstract: A method for distributed agent based non-expert simulation of manufacturing process behavior on a single-processor computer comprises the steps of: object modeling a manufacturing technique having a plurality of processes; associating a distributed agent with each the process; and, programming each the agent to respond to discrete events corresponding to the manufacturing technique, wherein each discrete event triggers a programmed response. The method can further comprise the step of transmitting the discrete events to each agent in a message loop. In addition, the programming step comprises the step of conditioning each agent to respond to a discrete event selected from the group consisting of a clock tick message, a resources received message, and a request for output production message.

Abstract: In the pyrolytic oil-production index method, or POPI method, the numerical values obtained by the application of the prior art POPI method are standardized or normalized. In another aspect, the POPI method and associated data are employed in combination with other empirically determined information to provide values of (1) the API gravity for the reservoir oil; (2) the Apparent Water Saturation (ASw) of the reservoir rock; and (3) the cementation and saturation exponents that are used in the Archie equation for calculating the water saturation in the oil-reservoir rock. This method results in the standardization of the numerical values derived by the POPI method. Applying the normalization or standardization process to the POPI method results in the conversion of the numerical value of POPIo for good oil-producing reservoir rock to a standard value.

Abstract: Invention maintains duplicate files in safe places. A SCAN computer program creates a TOKEN Table of an earlier file. The TOKEN Table reflects the indices of successive segments of the file and the exclusive-or (XR) and Cyclic redundancy check (CRC) products of the characters in each segment. An updated file is compared to the earlier file by comparing the XR and CRC products of segments in the updated file to the XR and CRC products in the TOKEN Table. On detecting matching products for identical segments, the next segments are compared. On mismatch, the segment (window) for the updated file is bumped one character and new XR and CRC products generated and compared. The indices of the TOKEN Table and the offsets from the start of the file of the first characters of the updated file matching segments are set forth in a Match Table.

Abstract: A device for synthesizing a reverse model of a system includes a first store storing bits representative of transition functions of the system, a second store storing bits representative of an estimate of transition functions of the reverse model, and processing system.

Abstract: In a logic simulation method, one of an algorithm level simulation and a register transfer level simulation is executed. The algorithm level simulation corresponds to an algorithm level description and the register transfer level simulation corresponds to a register transfer level description. The simulation is switched from one of the algorithm level simulation and the register transfer level simulation into the other in response to a switching instruction using a relation between states of the algorithm level description and states of the register transfer level description. The algorithm level description is associated with arithmetic and logic algorithm and not associated with logic circuits. The register transfer level description is associated with logic circuits.

Abstract: The invention relates to a method and apparatus for analyzing fluid flow while considering heat transfer effects and, in particular, a phase change from a molten state to a solid state. In particular, the method and apparatus may be applied to the analysis of an injection molding process for producing a molded polymer component from a thermoplastic or a thermosetting polymer. In one embodiment, the method may be used to determine pressure required to fill a mold cavity and pressure gradients introduced during filling and packing of the cavity of an injection mold. The results of these analyses may be used to determine the number and location of gates, to determine the best material for the component, and to optimize the process conditions used in the molding process.

Abstract: The present invention describes a system and method for independently verifying the Execution Rate of individual tasks by a device through simulation. Described is a situation in which a system has a main device through which data flows to and from other devices. Bus transfers must fall within required rates. A simulation of the configuration utilizes models of the various devices, including the “Main device”. This simulation is used to verify the data traffic and associated transfer rates. Data transfer includes random bursts, with randomly chosen periods between bursts. The data rate and data validity are measured during each burst period.

Abstract: A method and system for modeling rooms or chambers in a structure for intuitive and accurate estimation of process parameters (e.g., material and labor costs for performing the process) associated with the rooms. A graphical user interface to an estimation program enables an estimator to insert a model of a room and thereafter morph and mold the model to approximate the room undergoing estimation. The model is represented as a polyhedron having a plurality of planes that may be assigned attributes such as floors, walls and ceilings. During the morphing process, the modified and other affected planes of the polyhedron are continually revised to maintain the integrity of the closed volume represented,by the polyhedron.

Abstract: A method of automatically generating vector sequences for an observability based coverage metric supports design validation. A design validation method for Register Transfer Level (RTL) circuits includes the generation of a tag list. Each tag in the tag list models an error at a location in HDL code at which a variable is assigned a value. Interacting linear and Boolean constraints are generated for the tag, and the set of constraints is solved using an HSAT solver to provide a vector that covers the tag. For each generated vector, tag simulation is performed to determine which others of the tags in the tag list are also covered by that vector. Vectors are generated until all tags have been covered, if possible within predetermined time constraints, thus automatically providing a set of vectors which will propagate errors in the HDL code to an observable output. Performance of the design validation method is enhanced through various heuristics involving path selection and tag magnitude maximization.

Abstract: A design verification method for verifying hardware designs utilizing combinational loop logic. A design verification system is provided wherein a model checker receives both a mathematical representation of the functionality of a design and a set of properties against which the mathematical model is to be checked. If the design contains a combinational loop wherein the output directly depends on its own output and must be logically completed within a single bus cycle, then modifications to the model are undertaken. A minimal number of flip-flops are first added to the combinational loop in order to break up the combinational dependency. All of the states of a state machine model of the design are then supplemented with a twin state which is exactly the same as the original state. If the current state is an original state then the next cycle progresses the state machine to twin state of the particular original state.

Abstract: An information processing apparatus which pleases a user with a higher degree of entertainment property is disclosed. A graphic chip copies original image data stored in a VRAM into a buffer built therein so that the original image data may be stored into the buffer. Further, the graphic chip reverses those of the original image data in replacement areas of the image horizontally leftwardly and rightwardly and stores the thus reversed image data into the buffer. The graphic chip thereupon performs &agr; blending of the original image data and the reversed image data based on &agr; values of a table.

Abstract: A computer readable program product stores a role playing game which sets items of equipment provided to a player character in accordance with an operational input, links special abilities with the items of equipment, increases a level of mastery of an item of equipment of a player character in accordance with fight experience between the player character and an enemy character, sets an AP value for a special ability linked with an item of equipment in accordance with the level of mastery of the item of equipment, and allows the player character to use a special ability after the AP value of that special ability reaches a value for acquisition of that special ability.

Abstract: A method and apparatus for generating a covering set of test cases from a directed graph is provided. The directed graph includes nodes and edges connecting the nodes, and a test case is a path through the directed graph. To generate a partial set of test cases, a set of selected test cases is received. These test cases can be manually selected or they can be a maintained test case set. The edges or nodes on the directed graph (or requirements linked to nodes or edges) that are covered by the selected test cases are marked with an identifier. Test cases are then generated from the directed graph according to a coverage algorithm. Marked graph elements may, but need not, be included in the generated test cases. The resulting partial test case set together with the selected test cases satisfy the coverage criterion.

Abstract: An algorithm programmed into a computer permits the computer to automatically generate a two-dimensional profile curve of an electronically represented three-dimensional solid model without creating separate intersecting planes extending through the three-dimensional solid. The computer is configured to query the three-dimensional solid to identify faces on the three-dimensional solid. The query of the solid begins after a face edge is identified as a seed face and continues from the identified face to each adjacent revolved face circumscribing the solid. As each revolved face is located, a representative curve for the face is created in the two-dimensional plane.

Abstract: An objective is to provide a microcomputer, electronic equipment and emulation method which can realize the optimum circumstance of evaluation while saving the number of terminals. An external bus is shared between external and emulation memories. In the emulation mode, the access of CPU to an internal ROM is switched to the access of CPU to the emulation memory through an external bus. The emulation mode is turned ON or OFF through a mode selection terminal or mode selection register. The emulation memory is controlled by a control signal CNT2 different from a control signal CNT1 which controls the external memory. A memory read signal in CNT2 become active at a timing earlier than that of a memory read signal in CNT1. Thus, the instruction is fetched and decoded within one clock cycle. A mode selection terminal is further provided for selecting a mode of performing the boot from the emulation memory, internal ROM or external memory and a made of selecting OPT mode.