Abstract: An object of the present invention is to control incoming data to be received by an appropriate communication destination by using a main device to monitor a traffic state of a wireless LAN and a user login state. A main device (1) for performing call control call control of wireless telephone (8, 8) determines a transmission destination (transfer destination) of a call received from, for example, a traffic state of the wireless-LAN base station (2, 3) or a login state of the wireless telephone, and transmits data to, for example, a public network (6), a local-area network, or an IP telephone network. In addition, the main device (1) preliminarily transmits data-reception notifying mail to a reception destination to enable a user to select a data-receiving method.

Abstract: A method of decoding an encoded bitstream. The method includes performing a table lookup. Addresses into the table are generated using selected numbers of bits drawn from the bitstream in response to values stored in the table entries. A table entry may contain an index offset and a number of bits to extract from the bitstream. Alternatively, the table entry may contain the decode result. The value of a result tag in the entry signals which of the alternatives is contained in the entry. The table is recursively accessed until a portion of the bitstream is decoded. Any remaining portion of the bitstream is decoded similarly. An initial index into the table is determined from a number of bits of the bitstream corresponding to the length of the smallest code word in the codetable used to encode the bitstream.

Abstract: Available quadrature amplitude modulation (“QAM”) carriers transmittable by a base station to customer sites are substantially equally divided among the sites according to the expected quality of reception. ARQ transmissions from the sites are monitored as a measure of the quality of signals received by the sites. If the quality of received signals is unacceptable, the affected site is re-assigned to a higher quality QAM. In addition, if the quality of received signals is too high, the affected site is re-assigned to a lower quality QAM.

Abstract: Stable, robust, and high-resolution delta-sigma error feedback modulators, such as those used in digital-to-analog converters and phase-locked loops, include an L-order noise transfer function that is provided with L+1 high-order bits from a truncation element. The stability of such delta-sigma error feedback modulators is independent of the input signal. Moreover, the out-of-band gain of the noise transfer function need not be limited, which improves the resolution and the signal-to-noise ratio of the in-band signal.

Abstract: A ramp generator includes an array of capacitors having a common top plate that provides a ramp output signal. Each of the capacitors has a bottom plate switched sequentially between a low reference voltage and a high reference voltage in response to a value in a shift register. For an upward ramp, capacitors can be switched to their high reference voltages in succession, increasing the output voltage on the common top plate; for a downward ramp, capacitors can be switched to their low reference voltages in succession, decreasing the output voltage. The capacitors can be switched by a multi-bit shift register, each bit of which controls one capacitor's voltage. Each time a clock signal is applied to the shift register, a value in the shift register shifts another capacitor between its low and high reference voltages.

Abstract: A method and computer program for generating a K-bit Gray code comprises (a) selecting a M-bit Gray code number from a M-bit Gray code having a one-bit separation I and a two-bit separation J; (b) selecting a N-bit Gray code number from a N-bit Gray code, wherein K=M+N, M?N, and at least one of I and J is greater than, or equal to, 2N; (c) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a K-bit Gray code number; (d) generating the next 2N?1 sequential K-bit Gray code numbers, comprising (e) selecting a next M-bit Gray code number from the M-bit Gray code, (f) concatenating the selected M-bit Gray code number and the selected N-bit Gray code number to produce a next K-bit Gray code number, and (g) repeating steps (e) and (f); (h) selecting a next N-bit Gray code number from the N-bit Gray code; and (i) repeating steps (c) through (h).

Abstract: A method for providing an electronic business card to a contact via a cellular phone is disclosed. Several business card menu options are provided to a user of a cellular telephone. The cellular phone user enters business card information/data into the cellular phone utilizing the business card menu options. The business card data is stored locally on the cellular phone or in a service provider database. When the user is in communication via cellular phone with someone he wishes to provide his business card to, the user selects a menu item that activates the transmission of the electronic business card to the desired recipient's cellular phone.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: An encoder includes a linear offset amplifier, a linear analog to digital converter coupled to the linear offset amplifier, a switched offset amplifier, a switched analog to digital converter coupled to the switched offset amplifier, and a video controller. The video controller is coupled to both the linear and switched analog to digital converters. The video controller is configured to set both gains and offsets of the linear and switched analog to digital converters so that the gain and offset of the linear analog to digital converter is different than the gain and offset of the switched analog to digital converter.

Abstract: A predistortion circuit for a microwave amplifier and more particularly to predistortion circuit configured as a Doherty amplifier. The predistortion circuit is adapted to be coupled to a downstream Doherty amplifier to precompensate for the gain compression and phase expansion of the downstream Doherty amplifier as the input power level is increased while simultaneously reducing the intermodulation (IM) distortion. In order to provide precompensation, the precompensation circuit is operated at bias level to provide gain expansion and phase compression to cancel out the gain compression and phase expansion of the downstream Doherty amplifier to provide a higher overall linear power added efficiency (PAE).

Abstract: A switching device having a central actuator and two outer actuators disposed separately from the central actuator on two sides, wherein the central actuator is a cylindrical dial (23) supported rotatably and depressibly by a pair of spindle bearings (26) included in a base plate; the base plate (25) supporting the dial (23) is fitted in a frame; the outer actuators are pivotable in a direction approximately perpendicular to a direction in which the three actuators are arrayed and about a pivot approximately perpendicular to a direction in which operating surfaces of the outer acutators are pushed to press a contact (30) disposed on the frame; and each of the outer actuators has a to-be-supported piece (34) extending to a position where the outer actuator deviates from a lateral edge of the dial (23) in the rotating direction as viewed from the front.

Abstract: A D/A conversion method and D/A converter. First, an m-bit data is input, wherein the m-bit data includes upper n bit data and lower m?n bit data. Then, a first n bit data is obtained by transforming the upper n bit data. Finally, the upper n bit data is applied to an n-bit D/A converter for a first duration and the first n-bit data is applied to the n-bit D/A converter for a second duration, according- to the lower m?n bit data.

Abstract: An apparatus compensates for voltage and temperature variations on an integrated circuit with: a voltage sensor having a digital voltage output; a temperature sensor having a digital temperature output; a register coupled to the voltage sensor and the temperature sensor, the register adapted to concatenate the digital voltage output and the temperature output into an address output; and a memory device having an address input coupled to the address output of the register, the memory device being adapted to store one or more corrective vectors.

Abstract: A digital-to-analog converter (DAC) for use in high-speed wireless communications. The DAC of the invention comprises a plurality of current steering cells to bi-directionally provide a differential current output. When the DAC sets the differential current output to zero for example, each of the current steering cells establishes dummy branches between a pair of current sources and thereby prevents the current sources from floating. This in turn enables the DAC to operate with a higher update rate.

Abstract: In a digital amplifier, a time controller generates first and second selection signals for outputting any one of music data, a center output, and a lowest output to a P output and an N output based on a power ON/OFF signal and a start/stop signal, and also generates a third selection signal for determining whether a signal having the same phase as that of the P output is output to the N output or a signal obtained by inverting the P output is output to the N output. A data selection circuit determines data to be output to the P output and the N output based on the first and second selection signals. An output data register circuit converts parallel data determined by the data selection circuit into serial data to output the serial data into the P output. An output selection circuit determines the N output based on the third selection signal.

Abstract: A digital-to-analog conversion circuit of charge distribution type includes a plurality of capacitors having respective capacitances that increase in a sequential order, one end of the capacitors being commonly connected electrically. The circuit also includes a plurality of analog switches each for electrically connecting a reference potential corresponding to a digital signal inputted from outside to the other end of the corresponding capacitor. These analog switches have respective driving capacities that increase in a sequential order.

Abstract: An analog-to-digital converter that does not use an external clock signal to convert an incoming analog signal to a digital output signal including two or more comparators configured to receive an analog input signal, a digital-to-analog converter configured to produce a reference signal for the comparators, and asynchronous logic configured to sample comparator results and adjust a digital output signal accordingly.

Abstract: A method and circuit are provided for converting a digital signal to an analog signal in the form of a pulse width modulated (PWM) pulse (20). The PWM pulse is generated during an output cycle of a pulse generator to form a pulsetrain output of pulses at a fixed frequency whose widths are determined by dynamically changing digital input data. The method includes the steps of dividing the digital data signal into most significant bit (MSB) and least significant bit (LSB) portions. A PWM pulse is initiated at the beginning of an output cycle and continues while the MSB portion counts down in a counter (24). At the same time, the LSB portion of the digital data signal is converted to a precise phase delay signal which is a subcycle of an oscillator controlling the counter. This phase delay signal is generated after the termination of the MSB count, and halts the high period of the PWM pulse during the output cycle. When the output cycle ends, the process is repeated with the next digital signal.

Abstract: A method of providing an automatic gain control (AGC) in a receiver structure includes multiplying a received analogue signal with a predetermined gain setting to obtain an amplifier output signal, sampling the amplifier output signal, estimating the energy in the samples, calculating the average energy, computing the percentage of clipped samples, calculating the target energy value based on the average energy and the percentage of clipped samples and the gain setting, and applying the update receiver gain setting.

Abstract: A method for identifying particular characteristics of a physical system includes assigning codes information to the system based upon two distinct characteristics. The code increases in value, with increasing code numbers being assigned to combination of the characteristics in such a way that between any two adjacent code values, only one of the two characteristics change, and the increasing value only changes by one value level.