Abstract: A monolithic three dimensional charged coupled device (3D-CCD) which utilizes the entire bulk of the semiconductor for charge generation, storage, and transfer. The 3D-CCD provides a vast improvement of current CCD architectures that use only the surface of the semiconductor substrate. The 3D-CCD is capable of developing a strong E-field throughout the depth of the semiconductor by using deep (buried) parallel (bulk) electrodes in the substrate material. Using backside illumination, the 3D-CCD architecture enables a single device to image photon energies from the visible, to the ultra-violet and soft x-ray, and out to higher energy x-rays of 30 keV and beyond. The buried or bulk electrodes are electrically connected to the surface electrodes, and an E-field parallel to the surface is established with the pixel in which the bulk electrodes are located. This E-field attracts charge to the bulk electrodes independent of depth and confines it within the pixel in which it is generated.

Abstract: A method of routing power supply voltage electrodes and reference voltage electrodes which makes efficient use of chip area, maximizes decoupling capacitance, and reduces voltage drops due to electrode resistance is described. The two top wiring layers of an integrated circuit chip are used as power distribution layers to distribute the power supply voltage and reference voltage so that the power supply voltage bus electrode and reference voltage bus electrode are in separate wiring layers. The chip is partitioned into a number of sub-blocks with spaces between the sub-blocks. In a first wiring layer the power supply voltage bus electrode is routed so as to surround each of the sub-blocks. In a second wiring layer the reference voltage bus electrode is routed so as to surround each of the sub-blocks.

Abstract: A semiconductor device includes a semiconductor substrate having a trench in its surface, an insulating film in the trench, a doped conductive layer on the insulating film, a gate insulation film and a gate electrode on the doped conductive layer over the trench, and source and drain impurity regions in the surface of the semiconductor substrate at sides of the gate electrode.

Abstract: A method and apparatus for protecting hypersensitive microcircuits on the face of a semiconductor wafer from contamination and mechanical damage during die sawing and subsequent die handling operations include the provision of a plastic sheet having an array of protective domes formed into it, the array corresponding to the array of microcircuits on the wafer, and the temporary adhesion of the sheet to the face of the wafer such that each die in the wafer is covered by a respective one of the domes, with an associated one of the microcircuits protectively sealed therein. Die sawing is performed with the component side of the wafer facing up, the cut passing between the domes and through the thicknesses of both the domed sheet and the wafer such that each die is separated from the wafer, with a corresponding one other domes still attached to it. The domes may be removed later when the dies are located in a more benign environment by simply peeling them off the die.

Abstract: A method of producing a strained crystalline semiconductor microelectronic device(s). Microelectronic device(s) are formed within a membrane. The method includes the steps of straining a membrane along at least one axis and bonding the membrane to a base substrate.

Abstract: After forming a barrier film on a silicon-containing film including silicon as a main component, a high-melting-point metal film is deposited on the barrier film, so as to form a laminated structure including the silicon-containing film, the barrier film and the high-melting-point metal film. The laminated structure is subjected to a heat treatment at a temperature of 750° C. or more. The barrier film is formed by forming a first metal film of a nitride of a metal on the silicon-containing film; forming, on the first metal film, a second metal film of the metal or the nitride of the metal with a smaller nitrogen content than the first metal film; and forming, on the second metal film, a third metal film of the nitride of the metal with a larger nitrogen content than the second metal film.

Abstract: In the case of providing a contact hole (2a) in an insulting film (2) on the substrate (1), and forming a wiring on the insulting film to be connected to an exposed portion by the contact hole, a tin film (4) is formed on a location where the wiring is formed, and a paradium film (5) is formed on a location where the wiring is formed by immersing a portion where the tin film is provided in a solution containing a paradium ion (Pd2+). Then, the paradium film is used as a reaction start layer to form a copper film (6) by the electroless plating method. Furthermore, a second copper film may be formed by the electroplating by using the copper film as the feeder layer. By doing so, there is provided a semiconductor device wherein the diffusion of elements of the reaction start layer (the seed layer) into the film is prevented, a copper film having a small specific resistance and excellent conductivity formed with good reliability, and a higher integration can be provided with further fine wiring.

Abstract: A method of enriching the surface of a substrate with a solute material that was originally dissolved in the substrate material, to yield a uniform dispersion of the solute material at the substrate surface. The method generally entails the use of a solvent material that is more reactive than the solute material to a chosen reactive agent. The surface of the substrate is reacted with the reactive agent to preferentially form a reaction compound of the solvent material at the surface of the substrate. As the compound layer develops, the solute material segregates or diffuses out of the compound layer and into the underlying substrate, such that the region of the substrate nearest the compound layer becomes enriched with the solute material. At least a portion of the compound layer is then removed without removing the underlying enriched region of the substrate.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A transistor having an improved sidewall gate structure and method of construction is provided. The improved sidewall gate structure may include a semiconductor substrate (12) having a channel region (20). A gate insulation (36) may be adjacent the channel region (20) of the semiconductor substrate (12). A gate (38) may be formed adjacent the gate insulation (36). A sidewall insulation body (28) may be formed adjacent a portion of the gate (38). The sidewall insulation body (28) is comprised of a silicon oxynitride material. An epitaxial layer (30) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the semiconductor substrate (12) substantially outward of the channel region (20). A buffer layer (32) may be formed adjacent a portion of the sidewall insulation body (28) and adjacent the epitaxial layer (30).

Abstract: Methods and arrangements are provided for introducing nitrogen into a tunnel oxide layer within a stacked gate structure of a non-volatile memory cell. The nitrogen is advantageously introduced into only a select portion of the tunnel oxide, preferably nearer the source region of the memory cell. This prevents the unwanted or residual nitrogen from detrimentally affecting other devices within the semiconductor integrated circuit.

Abstract: A method for fabricating a semiconductor device in a substrate. Active regions are defined within the substrate using a thin oxide layer and a silicon nitride layer with portions of the silicon nitride layer being etched away to expose the thin oxide layer. Field oxide regions are formed over regions other than the defined active regions. These field oxide regions are located between the active regions. The remaining portions of the silicon nitride layer and the thin oxide layer are removed and a sacrificial oxide layer is then grown on the surfaces of the active regions. A first mask, a N-well mask, is formed for implanting N-type dopants. A buried layer implanted using P-type dopants with the first mask in place. Thereafter, the N-well regions are implanted. The first mask is removed and a second mask is formed to define regions for implanting P-well regions using P-type dopants. The P-well regions are implanted using P-type dopants.

Abstract: A method of making an IGFET includes providing a semiconductor substrate with an active region, forming a gate over the active region, forming displacement material segments over portions of the active region outside the gate, implanting a dopant into the gate, the displacement material segments and the active region using a single implant step, such that a peak concentration of the dopant is in the gate and the displacement material segments, and a light concentration of the dopant implanted through one of the displacement material segments forms a lightly doped drain region in the active region, and forming a source and a drain wherein the drain includes the lightly doped drain region. In this manner, the lightly doped drain region and heavy doping for the gate can be provided using a single implant step.