Abstract: Methods of fabricating an image sensor equipped with a lens are disclosed. The disclosed methods can attach a lens directly onto a device without fabricating a separate lens module in a fabrication process of an image sensor device by forming a concave groove on the bottom surface of the lens and coupling the device and the lens by alignment marks after forming a metal convex portion around a pixel array and forming a lens from a mobile material in the final step of device fabrication prior to performing a packaging process.

Abstract: A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.

Abstract: In a process of fabricating flip chip interconnection, a UBM layer is deposited on an I/O pad of a chip. The UBM layer includes a nickel layer. On the UBM layer is formed a tin-containing solder material. The chip is mounted on a carrier substrate by alignment of the bonding pad with a contact pad of the carrier substrate. A reflow process is performed to respectively turn the tin-containing solder material to a tin-containing solder bump and form a composite intermetallic compound on the nickel layer of the UBM to prevent its spalling.

Abstract: In producing a thin film transistor (TFT), an silicon oxide film is formed as an under film on a glass substrate, and then an amorphous silicon film is formed therein. A metal element which promotes crystallization of silicon is disposed in contact with a surface of the amorphous silicon film. A thermal processing for the amorphous silicon film is performed at a crystallization temperature of the amorphous silicon film or higher. At the thermal processing, a glass substrate is placed on an object having constant flatness. Cooling is performed to obtain a crystalline silicon film wherein the substrate is not distorted and deformed.

Abstract: A semiconductor manufacturing process wherein an organic antireflective coating is etched with an O2-free sulfur containing gas which provides selectivity with respect to an underlying layer and/or minimizes the lateral etch rate of an overlying photoresist to maintain critical dimensions defined by the photoresist. The etchant gas can include SO2 and a carrier gas such as Ar or He and optional additions of other gases such as HBr. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

Abstract: The present invention provides a method of manufacturing a semiconductor device that includes incorporation of a hydrogen isotope at a relatively high processing temperature during gate oxidation or polysilicon gate electrode deposition to maximize incorporation of hydrogen isotope at interfaces deliberately created during oxidation (such as graded oxidation) as multilayered poly/alpha-silicon deposition process.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: A method of forming a uniform collar oxide layer over an upper portion of a sidewall of a trench extending into a semiconductor substrate is disclosed. A silicon oxide layer and a mask layer are conformally formed on a single-crystal silicon substrate having a trench. A photoresist layer is formed on the mask layer, a part of the photoresist layer is then removed to make the top surface of the photoresist layer lower than the top surface of the single-crystal silicon substrate with a distance. After the mask layer and the silicon oxide layer, which are not covered by the remaining photoresist layer, are removed, the remaining photoresist layer is removed. Then, an ion implantation process is proceeded to make the oxidation rates in the (110) and (100) orientations existing in the sidewall of the trench equal to each other. After the sidewall of the trench is treated, a local oxidation is executed to form a uniform collar oxide layer.

Abstract: A process for manufacturing a semiconductor memory device includes double polysilicon level non-volatile memory cells and shielded single polysilicon level non-volatile memory cells in the same semiconductor material chip. A first memory cell includes a MOS transistor having a first gate electrode and a second gate electrode superimposed and respectively formed by definition in a first and a second layer of conductive material. A second memory cell is shielded by a layer of shielding material for preventing the information stored in the second memory cell from being accessible from the outside. The second memory cell includes a MOS transistor with a floating gate electrode formed simultaneously with the first gate electrode of the first cell by definition of the first layer of conductive material. The layer of shielding material is formed by definition of the second layer of conductive material.

Abstract: A method of fabricating a semiconductor device capable of fabricating a semiconductor device including a polycrystalline semiconductor film having excellent characteristics with a high yield is provided. A first amorphous semiconductor film is formed on a substrate. A conductive film is formed on the first amorphous semiconductor film. The conductive film is irradiated with an electromagnetic wave such as a high-frequency wave or a YAG laser beam thereby making the conductive film generate heat and converting the first amorphous semiconductor film to a first polycrystalline semiconductor film through the heat. Thus, polycrystallization is homogeneously performed without dispersion through the heat from the conductive film irradiated with the electromagnetic wave. Consequently, an excellent first polycrystalline silicon film can be formed with an excellent yield.

Abstract: Thin films are formed by atomic layer deposition, whereby the composition of the film can be varied from monolayer to monolayer during cycles including alternating pulses of self-limiting chemistries. In the illustrated embodiments, varying amounts of impurity sources are introduced during the cyclical process. A graded gate dielectric is thereby provided, even for extremely thin layers. The gate dielectric as thin as 2 nm can be varied from pure silicon oxide to oxynitride to silicon nitride. Similarly, the gate dielectric can be varied from aluminum oxide to mixtures of aluminum oxide and a higher dielectric material (e.g., ZrO2) to pure high k material and back to aluminum oxide. In another embodiment, metal nitride (e.g., WN) is first formed as a barrier for lining dual damascene trenches and vias. During the alternating deposition process, copper can be introduced, e.g.

Abstract: Within a method for forming a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a patterned conductor layer having a topographic variation at a periphery of the patterned conductor layer. There is then formed over the substrate and passivating the topographic variation at the periphery of the patterned conductor layer a planarizing passivation layer formed of a thermally reflowable material. There is then formed upon the planarizing passivation layer a dimensionally stabilizing layer. Finally, there is then thermally annealed the microelectronic fabrication to form from the planarizing passivation layer a thermally annealed planarizing passivation layer. By employing formed upon the planarizing passivation layer the dimensionally stabilizing layer, there is attenuated within the thermally annealed planarizing passivation layer replication of the topographic variation at the periphery of the patterned conductor layer.

Abstract: A method of making a semiconductor device (10) having a low permittivity region (24) includes forming a first layer (30/42) over a surface of a trench (20), and etching through an opening (70) in the first layer that is smaller than a width (W2) of the trench to remove a first material (38) from the trench. A second material (44) is deposited to plug the opening to seal an air pocket (40) in the trench. The low permittivity region features air pockets with a high volume because the small size of the opening allows the second material to plug the trench without accumulating significantly in the trench.

Abstract: A multilayer flexible wiring board, suited for mounting semiconductor elements. The flexible wiring board is fabricated in the following manner. A flexible wiring board piece having a metal wiring, in which a metal coating is exposed on at least a part of surface of the metal wiring, is adhered to another flexible wiring board piece having a metal projection on which a metal coating is formed. One of or both of the metal coatings on the metal wiring and the metal projection is composed of a soft metal coating a surface of which has a Vickers' hardness of 80 kgf/mm2 or lower. The metal coating of the metal wiring contacts with the metal coating of said metal projection and ultrasonic wave is applied thereto to connect the metal wiring with the metal projection.

Abstract: A chemical vapor deposition process for depositing tungsten films having small grain size is provided. The process involves depositing a nucleation layer having very small nuclei that are closely spaced so that there are few vacancies on the surface. Such a nucleation layer results in a film with small grains after the subsequent deposition of bulk layers. The temperature of the substrate can be increased during deposition of the nucleation layer and then lowered for deposition of the bulk layer to produce a small grain tungsten film. Additionally, the thickness of the nucleation layer can be controlled, and the deposition chamber pressure and silage flow rates can also be controlled to achieve the desired nucleation layer before deposition of the bulk layers.

Abstract: The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.

Abstract: A new method of producing strained crystalline semiconductor microelectronic devices. Microelectronic devices can either be formed within a membrane, prior to straining or processed after straining. The method includes the steps of straining a membrane along at least one axis and straining using wafer-bonding techniques.

Abstract: A process for effectively reducing reactivity of a surface of a semiconductor substrate is described. The process includes: (1) oxidizing in an oxidizing environment the semiconductor substrate surface, the semiconductor substrate having a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein the oxidizing and the annealing of the semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. A surface passivation apparatus is also described. The apparatus includes: a heating source for heating a substrate surface; an ozone generator; and a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein the ozone generator is configured to produce ozone within the chamber using the gas composition.

Abstract: The invention utilizes introductions of oxygen and hydroxyl to perform an in situ steam generated process to reoxidize a conventional sidewall oxide layer and density the oxide in a shallow trench isolation. The ISSG process renders the conventional sidewall oxide layer much less stress and encroachment. The electrical property of the active regions and the isolation quality between the active regions can be assured. The ISSG process can densify the oxide in a shallow trench isolation to prevent the oxide from being lost in the following clean process.

Abstract: Disclosed herein is a technique which performs the thinning of a wafer and the separation thereof from a support substrate with high yields and in a short time. Described specifically, a hole-free support substrate is bonded to a second surface of a support substrate having holes with an adhesive layer melted by heating so as to bloc the holes. A wafer is bonded to a first surface of the support substrate having the holes with an adhesive layer melted by solvent. The wafer is thinned by grinding and etching. The adhesive layer is melted by heating and the support substrate having the holes is slid with respect to the hole-free support substrate to thereby separate the support substrate having the holes from the hole-free support substrate. Further, the adhesive layer is melted by solvent from the holes defined in the support substrate having the holes to thereby separate the wafer from the support substrate having the holes.