Patents Examined by Khanh Nguyen
  • Patent number: 8574435
    Abstract: Disclosed herein is an advanced treatment system processing contaminated water or fouled water/waste water, and particularly, a system for membrane fouling control and reduction in the amount of sludge producing in a membrane combined-type fouled water/waste water advanced treatment system, and more particularly, a system capable of making sludge soluble using plasma and then re-utilizing cell byproducts of destructed sludge as a supply source of external carbon source, and possibly capable of removing a cake layer formed on a membrane using each kind of radical and ozone generated by plasma.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: November 5, 2013
    Assignees: Hoseo University Academic Cooperation Foundation, Kumkang Environmental Engineering Co., Ltd.
    Inventors: In Soung Chang, Ji Sun Lee, Seun Young Joung, Cheol Ku Lee
  • Patent number: 8475725
    Abstract: A method and energy-efficient apparatus for the treatment of liquids through the joint use of a gas mixture-oxidizing agent and UV radiation. This method uses an excimer UV lamp performing two actions affecting the liquid and changing its properties with UV radiation and the generation of a gas mixture containing strong oxidizing agents for influence on the liquid, disinfection and purification of the liquid being treated from contaminants. The apparatus incorporates energy efficient design features to reduce energy consumption and operational costs, as well as an excimer lamp design that improves performance parameters to surpass and outlast existing devices. Unique electrode designs, cleaning systems, and materials combine to create a state-of-the-art liquid treatment apparatus that exceeds existing industrial analogs and norms.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: July 2, 2013
    Assignee: East Coast Distribution, Inc.
    Inventors: Alexander Antipenko, Dmitry Budovich, Richard H. Sakaji, Alexander Medvedev, Eugene Veklerov, Vladimir Rakhamimov
  • Patent number: 8465613
    Abstract: Tooling apparatus for forming a composite charge into a contoured composite blade stringer includes an elongate punch and an elongate die flexible along their lengths. The charge is press formed by using the punch to drive the charge into the die. The punch and the die are mounted between a pair of flexible plates. A press coupled with the plates contours the charge by bending the plates into a desired contour.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: June 18, 2013
    Assignee: The Boeing Company
    Inventors: Daniel M. Rotter, Michael R. Chapman, Brad A. Coxon, Paul E. Nelson
  • Patent number: 8460499
    Abstract: A labeling machine for the dispensing of labels, such as self-adhesive labels, on objects, such as containers or bottles. The labeling machine has an arrangement for the generation of a defined strip tension of the labeling material over its strip length between a looper and a dispensing edge, and for the generation of a defined strip tension of the backing material over at least a part of its strip length between the dispensing edge and a receptacle for the backing material.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: June 11, 2013
    Assignee: KHS GmbH
    Inventors: Holger Stenner, Frank Putzer
  • Patent number: 8444801
    Abstract: An anodic bonding method of anodically bonding a base wafer 10 and a lid wafer 11 includes:(1) superimposing the base wafer 10 and the lid wafer 11 onto each other in a direction where a bonding film 9 faces a cavity C; (2) subsequent to the superimposition step, pressurizing and holding the base wafer 10 and the lid wafer 11 in a vacuum state in the superimposition direction; and (3) subsequent to the pressurizing step, partitioning and setting a plurality of intended bonding areas A1, A2, A3 and A4 in a concentric form on a contacting surface where the base wafer 10 and the lid wafer 11 are in contact with each other and applying a DC voltage to each of the plurality of intended bonding areas A1, A2, A3 and A4.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: May 21, 2013
    Assignee: Seiko Instruments Inc.
    Inventor: Kiyoshi Aratake
  • Patent number: 8337739
    Abstract: Methods of fabricating a polymeric implantable device from a PLLA/PDLA blend such as a stent with improved fracture toughness are disclosed. The blend is melt processed to allow formation of stereocomplex crystallites, which are nucleation sites for crystal growth. A polymer construct is formed from the melt processed blend and device is formed from the polymer construct. The stereocomplex crystallites result in an in increase in nucleation density and reduced crystal size, which increases fracture toughness of the formed device.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: December 25, 2012
    Assignee: Abbott Cardiovascular Systems Inc.
    Inventors: Yunbing Wang, James Oberhauser
  • Patent number: 8330547
    Abstract: An exemplary apparatus is disclosed that comprises a plurality of voltage to current transducers to convert an input signal voltage into a plurality of input signal currents and a cascode stage. The cascode stage is coupled to the voltage to current transducers to provide amplifier gain control. The cascode stage comprises a thin gate oxide transistor and a thick gate oxide transistor.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: December 11, 2012
    Assignee: QUALCOMM, Incorporated
    Inventor: Devavrata V Godbole
  • Patent number: 8279005
    Abstract: There is provided a method and apparatus for maintaining a bias current that flows through two transistors at a target level. The two transistors are both connected to form a series network between positive and negative voltage supply terminals. The bias current flows through the two transistors when the circuit is at equilibrium, and the threshold voltage of the transistors is controlled by controlling the voltage that is applied to the transistors bulk terminals. In addition to the two transistors, there is provided a control circuit that measures a circuit parameter that is indicative of the level of bias current flowing through the two transistors. In response to the measured parameter, the control circuit adjusts the bulk voltage levels of the two transistors so as to alter the transistors threshold voltages and maintain the level of bias current at a target level.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: October 2, 2012
    Assignee: NXP B.V.
    Inventors: Johannes H. A. Brekelmans, Lorenzo Tripodi
  • Patent number: 8212616
    Abstract: The invention concerns a biasing circuit for controlling the current flowing through a differential pair (102, 104) comprising: a first branch comprising a first resistor (306), a first transistor device (308) and a second transistor device (310) coupled in series; a second branch comprising a second resistor (312), a third transistor device (314) and a fourth transistor device (316) coupled in series, a control node of the third transistor device being coupled to a first node (324) between the first resistor and the first transistor device, and a control node of the first transistor device being coupled to a second node (322) between the second resistor and the third transistor device; and an operational amplifier (318) having an output node coupled to control nodes of the second and fourth transistor devices, said output node providing a output signal (Vc) for controlling the current flowing through said differential pair.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: July 3, 2012
    Assignee: STMicroelectronics SA
    Inventor: Eoin Ohannaidh
  • Patent number: 8193856
    Abstract: An amplifier (V) for an integrated circuit amplifier circuit (IC) having a switched capacitor circuit (Cs, Cf) includes a capacitor for frequency compensation (CC1) that is connected in parallel to an amplifier stage (V2). This amplifier is advantageous because at least one second capacitor for frequency compensation (CC2) is selectively connected in parallel to the first capacitor for frequency compensation (CC1) via a switch controlled by a capacitor switching signal (clk).
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: June 5, 2012
    Assignee: Trident Microsystems (Far East) Ltd.
    Inventors: José Manuel Garcia González, Norbert Greitschus
  • Patent number: 8193863
    Abstract: According to one embodiment, a first transistor is connected between a first power supply rail and an output unit. A second transistor is connected between the output unit and a second power supply rail. A gm amplifier includes an input unit and first and second output terminals and amplifies a difference between a signal input to the input unit and a reference voltage. First and second current mirror circuits are connected to be vertically stacked between the first rail and the first terminal as well as a gate of the second transistor. Third and fourth current mirror circuits are connected to be vertically stacked between the second rail and the second terminal as well as a gate of the first transistor. The gate of the first transistor is connected to the first and second circuits. The gate of the second transistor is connected to the third and fourth circuits.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroyuki Tsurumi
  • Patent number: 8183916
    Abstract: A non-inverting amplifier includes an operational amplifier, an input resistor, and a feedback resistor. The operational amplifier amplifies and outputs a difference between an input voltage and a voltage of a control node. The input resistor is connected between a reference voltage port and the control node. The feedback resistor is connected to an output port of the operational amplifier and the control node. The non-inverting amplifier supplies a control current to the control node for controlling an offset voltage of the output port.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: May 22, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Woog Byon
  • Patent number: 8183920
    Abstract: A variable gain amplifier includes a first common mode (CM) node configured to receive a first differential signal of a pair of differential signals. A first regulator couples to the first CM node, the first regulator being configured to generate a first CM offset. A second CM node is configured to receive a second differential signal of the pair of differential signals. A second regulator couples to the second CM node, the second regulator being configured to generate a second CM offset. In one embodiment, the first CM offset and the second CM offset together comprise a net CM offset, the net CM offset being configured to replace a current source net offset.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: May 22, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jieming Qi, David W. Boerstler, Minhan Chen, Hayden C. Cranford, Jr.
  • Patent number: 8183924
    Abstract: An input stage receives a differential input signal at first and second input nodes and provides a differential output current at first and second output nodes. The differential output current includes a component taken from the input nodes through first and second impedances, and an additional component generated in response to a sample of the voltage of the differential input signal. A transconductance cell having cross-coupled inputs may generate the additional component of the output current.
    Type: Grant
    Filed: June 3, 2010
    Date of Patent: May 22, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Barrie Gilbert
  • Patent number: 8183919
    Abstract: A power amplifier includes an inverter amplification section configured to amplify AC components and remove DC components from at least one input signal, an impedance matching section configured to match an impedance of a transmission path of the at least one input signal amplified by the inverter amplification section, and an amplification section configured to amplify an impedance-matched signal from the impedance matching section according to a predetermined gain. The inverter amplification section includes at least one P-channel metal-oxide semiconductor field effect transistor (MOS FET) having a gate configured to receive the at least one input signal and at least one N-channel MOS FET having a gate configured to receive the at least one input signal. The at least one P-channel MOS FET and the at least one N-channel MOS FET are serially connected.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 22, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Jean Song, Shinichi Iizuka, Youn Suk Kim, Hyo Kun Bae, Sang Hee Kim, Jun Goo Won, Joong Jin Nam, Ki Joong Kim, Jae Hyouck Choi
  • Patent number: 8183927
    Abstract: According to one embodiment, a variable attenuator is arranged in an input stage, a plurality of transistors are cascaded on the later part of this variable attenuator, temperature sensors are arranged in the vicinity of two or more of the plurality of transistors to detect temperatures, the amount of gain change of the plurality of transistors is calculated from the temperature detection results individually obtained by the temperature sensors, the variable attenuator is controlled in such a manner as to reduce the amount gain change so that the input signal level can be controlled, and thereby the gain that tends to vary in accordance with temperature changes can be stabilized.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryo Mochizuki
  • Patent number: 8183929
    Abstract: In accordance with an exemplary embodiment of the present invention, a Doherty amplifier is provided for applications in radio frequency, microwave, and other electronic systems. An exemplary Doherty amplifier comprises a first MMIC having a first power detector, and a second MMIC having a second power detector. The first MMIC and the second MMIC are structurally identical. Furthermore, the first MMIC is configured as a carrier amplifier and the second MMIC is configured as a peaking amplifier. In the exemplary embodiment, an amplifier control bias of the carrier amplifier is a function of the power detected by the first power detector and an amplifier control bias of the peaking amplifier is a function of the power detected by the second power detector. The ability to assemble a Doherty amplifier using a single MMIC product results in a simple and less expensive manufacturing process.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: May 22, 2012
    Assignee: ViaSat, Inc.
    Inventor: Christopher D. Grondahl
  • Patent number: 8174315
    Abstract: According to an embodiment, a method is provided that includes: adapting the impedance of the load dependent on working conditions of the active device using a controllable output-side adaptation network coupled between an output-side terminal of a transformer and an output-side node, to generate an adapted impedance of the load, adjusting the adapted impedance independent of the working conditions of the active device, using the transformer including a first inductor having a first terminal to receive the output of the active device via the input-side node, a second inductor having an output-side terminal, where the second inductor is magnetically coupled to the first inductor.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: May 8, 2012
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Tobias Mangold, Andreas Weisgerber
  • Patent number: 8174318
    Abstract: Apparatus and methods are disclosed, such as those involving a transconductance amplifier. One such apparatus includes a transconductance amplifier comprising an input to receive an input voltage signal, and an output to provide an output current signal at least partly in response to the input voltage signal. The apparatus also includes a linearizer configured to remove non-linearity in the output current signal such that the output current signal is substantially linear when the input voltage signal is within a range; and a current booster configured to add a current to the output current signal such that the output current signal is substantially linear when the input voltage signal is outside the range. The current booster allows the amplifier to have a linear response to a larger voltage swing without adding noise.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: May 8, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Edmund Balboni
  • Patent number: 8164384
    Abstract: A radio frequency (RF) circuit includes a power supply configured to generate a plurality of voltages, a plurality of power amplifiers, each having an RF output port and a power supply input port, a switch network having a plurality of input ports coupled to the power supply and a plurality of switch network output ports coupled to the power supply input ports of the plurality of power amplifiers, wherein the switch network is configured to output selected ones of the plurality of voltages from the plurality of switch network output ports, at least two of the switch network output port voltages capable of being different ones of the plurality of voltages, and an RF power combiner circuit having a plurality of input ports coupled to RF output ports of the plurality of power amplifiers and an output port at which is provided an output signal of the RF circuit.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: April 24, 2012
    Assignee: Massachusetts Institute of Technology
    Inventors: Joel L. Dawson, David J. Perreault, SungWon Chung, Philip Godoy, Everest Huang