Patents Examined by Khanh Tran
-
Patent number: 7099372Abstract: Disclosed is a method for operating a code division multiple access communications system, and a system that operates in accordance with the method. The method operates within a coverage area of a base station by assigning a set of spreading codes to individual ones of a plurality of subscriber stations and then, during transmissions within the cell, by periodically hopping amongst spreading code within the set of spreading codes such that at any given time no two subscriber stations operate with the same spreading code. The set of spreading codes may include the all one's spreading code. The step of periodically hopping preferably changes from a currently used spreading code to a next spreading code at a symbol rate or at a multiple of the symbol rate.Type: GrantFiled: October 24, 2001Date of Patent: August 29, 2006Assignee: L-3 Communications CorporationInventors: Leon L. Nieczyporowicz, Richard B. Ertel, Thomas R. Giallorenzi, Eric K. Hall
-
Patent number: 7099402Abstract: A transmitter 108 converts a complex baseband signal 140 having I and Q quadrature signal components 141 and 142 for transmission by an antenna 114. An intermediate frequency based complex-to-real up-converter 130 uses subsampling to convert the complex baseband signal 140 into a real digital signal 144 having digital signal representations 174. An intermediate frequency based bandpass filtering digital-to-analog converter 132 uses Delta-Sigma, bandpass techniques to convert the real digital signal 144 into a first analog signal 146 having analog signal representations 182. A post-conversion bandpass filter 134 isolates and boosts the signal-to-noise ratio of a selected analog signal representation 186 to output a second analog signal 148 having a post-filtered selected analog signal representation 192. A tracking bandpass filter 136 further bandpasses and up-converts the second analog signal 148 to output a transmittable signal 150 having a tracking-filtered selected analog signal representation 196.Type: GrantFiled: August 19, 2002Date of Patent: August 29, 2006Assignee: Qualcomm IncorporatedInventor: Steven M. Mollenkopf
-
Patent number: 7095795Abstract: A multi-rate transmission apparatus wherein components operate with a single clock from the outside and, even if the modulation system and the coding rate are varied arbitrarily by switching of the modulation operation mode similarly from the outside, transmission data can be allocated to modulation data and transmitted in response to the variation of the modulation system and the coding rate only with the clock signal from the outside. The multi-rate transmission apparatus includes a data processing section for reading in data with a bit width suitable for the modulation system, a coding unit for performing coding processing parallelly for the data read in by the data processing section, and a transmission section for transmitting the data, for which the coding processing has been performed, in response to the variation of the modulation system and the coding rate.Type: GrantFiled: March 31, 2000Date of Patent: August 22, 2006Assignee: NEC CorporationInventor: Mitsuhiro Agehari
-
Patent number: 7095808Abstract: A method of compressing a puncture mask information is disclosed, the method comprising making a delayed puncture mask by deleting the last k bits of the puncture mask; and appending k zeros to the beginning of the puncture mask; making a differential puncture mask by XORing the delayed puncture mask with the puncture mask; and compressing the differential puncture mask.Type: GrantFiled: August 16, 2000Date of Patent: August 22, 2006Assignee: Broadcom CorporationInventor: Aki Shohara
-
Patent number: 7092458Abstract: A BPSK phase detection unit assumes that an input signal is a BPSK modulated signal in detecting a phase error of a recovered carrier and an 8PSK phase detection unit assumes that the input signal is an 8PSK modulated signal in detecting the phase error of the recovered carrier. An 8PSK frequency detection unit assumes that the input signal is an 8PSK modulated signal in detecting a frequency error of the recovered carrier. A selector selects the phase error detected by the BPSK phase detection unit or the phase error detected by the 8PSK phase detection unit. A carrier recovery unit recovers a carrier by adjusting a phase of the input signal, based on the selected phase error and the frequency error.Type: GrantFiled: March 23, 2001Date of Patent: August 15, 2006Assignee: Renesas Technology Corp.Inventors: Lap Shing Chan, Shuji Murakami
-
Patent number: 7092460Abstract: In a stereo demultiplexer receiving a frequency demodulated stereo-multiplex signal (m(t)) which comprises at least a stereo-difference signal (md(t)), a stereo-sum signal (ms(t)) and a pilot carrier, a PLL-circuit (4) to recover the pilot carrier and/or at least one harmonic thereof receives the sampling rate decimated stereo-sum signal (ms(t)) as input signal, which is sampling rate decimated by a decimation factor of D. Therefore, the sampling rate decimation filter in the sum path is used for the sampling rate decimation to generate the 2nd harmonic or any other harmonic of the pilot carrier. This sampling rate decimation filter is available anyway and therefore the sampling rate decimation of the pilot carrier can be performed without an additional filter.Type: GrantFiled: October 18, 2000Date of Patent: August 15, 2006Assignee: Sony Deutschland GmbHInventor: Jens Wildhagen
-
Patent number: 7088790Abstract: In demodulation of a FSK signal, a circuit for detecting a center level of said signal and correcting an error thereof is provided. Said circuit can accomplish the detection of the center level correctly always even if there exist cords with various lengths in a length of “1” or “0” of a synchronizing signal at beginning of communication and during communication, and yet frequency variation happens at that time. Said circuit has sample hold circuits SH1 and SH2 each of which are provided so as to correspond to “1” and “0” of an input demodulated data signal. In said circuit a center level value is an average value of voltages held in said sample hold circuits when said signal changes from “1” to “0” or “0” to “1” and a center level value is obtained by adding or subtracting a voltage of ½ of difference between two hold voltages held in another sample hold circuit SH3 to or from a hold voltage in a receiving side at present time when said signal keeps “1” or “0” continuously.Type: GrantFiled: December 23, 2002Date of Patent: August 8, 2006Assignee: General Research of Electronics, Inc.Inventor: Kazuo Kawai
-
Patent number: 7088791Abstract: Systems and methods are provided for performing signal processing on communication data utilizing scale reduced Fast Fourier Transform computations. The present invention provides scaling in a Fast Fourier Transform computation at stages where it is determined that bit growth is present and omits scaling at stages where it is determined that bit growth is absent. The determination is based on the characteristics of the input signal. The determination can be made off-line by modeling and/or simulation or in real-time by analyzing the input signal to determine stages at which bit growth is present and/or absent and setting the stage scaling accordingly.Type: GrantFiled: October 19, 2001Date of Patent: August 8, 2006Assignee: Texas Instruments IncorporatedInventor: David Patrick Magee
-
Patent number: 7085315Abstract: A method and apparatus for digital demodulation for use in a wireless communication device include processing that begins by performing a fast Fourier transform to convert a plurality of time domain symbol components representing inbound data into a plurality of frequency domain symbol components. The processing continues by frequency domain equalizing at least some of the plurality of frequency domain symbol components based on a dynamic compensation control signal to dynamically compensate for adverse transmission characteristics of the plurality of time domain symbol components. The processing then continues by generating a plurality of estimated symbols and a plurality of error values for the plurality of compensated frequency domain symbol components.Type: GrantFiled: April 15, 2002Date of Patent: August 1, 2006Assignee: VIXS, Inc.Inventor: James R Kelton
-
Patent number: 7085336Abstract: A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.Type: GrantFiled: June 5, 2001Date of Patent: August 1, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-bae Lee, Kyu-hyoun Kim
-
Patent number: 7085325Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.Type: GrantFiled: August 20, 2002Date of Patent: August 1, 2006Assignee: Texas Instruments IncorporatedInventors: Peter Aberl, Ralf Eckhardt
-
Patent number: 7079616Abstract: The use of a PLL including a phase detector responsive to the phase difference between an input signal and a feedback signal and which pilots an oscillator in function of this difference, is envisaged. The PLL also includes a feedback path that is responsive to the signal generated by the oscillator and which generates said feedback signal via at least one divider with a variable division ratio. The division ratio of said divider is modulated via a sigma-delta modulator, the input of which is fed with a triangular-wave modulating signal. The preferred application is that of a spread spectrum clock generator (SSCG) for digital electronic systems.Type: GrantFiled: August 19, 2002Date of Patent: July 18, 2006Assignee: STMicroelectronics S.R.L.Inventors: Corrado Castiglione, Massimo Scipioni, Carlo Alberto Romani
-
Patent number: 7079596Abstract: A quadrature demodulator 408? and a quadrature modulator 908? convert a reception intermediate frequency signal 151 into reception baseband signals 157 and 158, and also convert transmission baseband signals 657 and 658 into a transmission intermediate frequency signal 651, respectively. While local oscillation signals having frequencies suitable for the respective bands are outputted from a commonly used local oscillator 111, such a local oscillation signal obtained by shifting a phase thereof ?/2 by a phase shifter 412 is supplied to one mixer of quadrature mixers 109 and 609, and such a signal obtained by inverting, or not inverting the plurality of the local oscillation signal by an exclusive OR gate circuit 413 in response to a band switching signal 153 is supplied to the other mixer of quadrature mixers 110 and 610.Type: GrantFiled: March 24, 2000Date of Patent: July 18, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Yasuaki Namura
-
Patent number: 7079584Abstract: Modulators for switched or switched and combined Orthogonal Frequency Division Multiplexed (OFDM), Code Division Multiple Access (CDMA), Spread Spectrum, Time Division Multiple Access (TDMA), cross-correlated and filtered systems. A first modulation circuit for receiving input OFDM baseband signals and a second modulation circuit for receiving input in-phase and quadrature-phase cross-correlated baseband signals, TDMA signals, spread spectrum signals, CDMA signals or other filtered signals. One of the switched or combined modulated Radio Frequency (RF) signals and the other switched or combined modulated RF signals are provided to one or more selected transmitters.Type: GrantFiled: April 14, 2005Date of Patent: July 18, 2006Inventor: Kamilo Feher
-
Patent number: 7079589Abstract: A communications system interleaves control pulses between the transitions in a serial bit stream to form an interleaved signal. The serial bit stream has a series of transitions and a series of gaps between transitions where a transition can not occur. An interleaver identifies gaps in the serial bit stream, and inserts the control pulses in the gaps to form the interleaved signal. The interleaved signal reduces the pin count when the interleaved signal is transmitted between chips.Type: GrantFiled: June 10, 2002Date of Patent: July 18, 2006Assignee: National Semiconductor CorporationInventors: Dragan Maksimovic, James Thomas Doyle
-
Patent number: 7075976Abstract: A tri-state transmitter drives a data line to a first state if a first data signal is a logic zero and releases the data line to a second state if the first data signal is a logic one. The tri-state transmitter also drives the released data line to a third state if the first data signal is a logic one and the second data signal is a logic one.Type: GrantFiled: March 19, 2001Date of Patent: July 11, 2006Assignee: Cisco Technology, Inc.Inventor: Li T Wang
-
Patent number: 7076010Abstract: The current invention provides a method and apparatus for time domain equalization in an XDSL modem. A received communication channel is analyzed to determine the highest frequency component thereof. Typically, there is an inverse relationship between the length of a subscriber line and the highest frequency component over which communications can be supported. In response to the frequency determination, the sampling rate for the channel is reduced to the lowest sample rate consistent with maintaining signal integrity on the highest frequency component of the channel. The sampling rate reduction may accomplished in the analog portion of the receive path, e.g. the analog-to-digital converter (ADC) or in a digital decimator coupled thereto. Concurrently the demodulator complexity is also scaled back. Where the XDSL protocol is digital multi-tone (DMT) the input sample size to the discrete Fourier transform (DFT) engine is reduced accordingly.Type: GrantFiled: June 6, 2001Date of Patent: July 11, 2006Assignee: Ikanos Communication, Inc.Inventors: Sam Heidari, Raminder S. Bajwa, Behrooz Rezvani, Dale Smith, Prem Ramaswamy
-
Patent number: 7072421Abstract: A digital signal processor generates in-phase, quadrature-phase and amplitude signals from a baseband signal. A modulator modulates the in-phase and quadrature-phase signals to produce a modulated signal. A phase locked loop is responsive to the modulated signal. The phase locked loop includes a controlled oscillator having a controlled oscillator input. An amplifier includes a signal input, amplitude control input and an output. The signal input is responsive to the controlled oscillator output and the amplitude control input is responsive to the amplitude signal. The phase locked loop that is responsive to the modulated signal includes a controlled oscillator output and a feedback loop between the controlled oscillator input and the controlled oscillator output. The feedback loop includes a mixer that is responsive to a local oscillator. The modulator may be placed in the phase locked loop.Type: GrantFiled: December 22, 2000Date of Patent: July 4, 2006Assignee: Telefonaktiebolaget L.M. EricssonInventors: Erik Bengtsson, Aristotle Hadjichristos, Scott R. Justice
-
Patent number: 7065136Abstract: A receiver (24) comprises a non-equalizing demodulator (48), an equalizing demodulator (46) and an output control selector (50). The non-equalizing demodulator (48) receives a modulated signal (44) and demodulates the modulated signal (44) to produce a first digital bit stream (54). The equalizing demodulator (46) receives the modulated signal (44) and equalizes and demodulates the modulated signal (44) to produce a second digital bit stream (52). The output control selector (50), coupled to the non-equalizing demodulator (48) and the equalizing demodulator (46), selectively delivers a first one of the first digital bit stream (54) and the second digital bit stream (52) for at least a predetermined period of time (30) before selectively delivering a second one of the first digital bit stream (54) and the second digital bit stream (52) responsive to a predetermined decision criterion (e.g., bit error rate 68).Type: GrantFiled: November 20, 2000Date of Patent: June 20, 2006Assignee: Freescale Semiconductor, Inc.Inventors: James L. Porter, John W. Diehl, Wayne H. Bradley
-
Patent number: 7061991Abstract: The present invention is related to methods and apparatus that can advantageously reduce a peak to average signal level exhibited by single or by multicarrier multibearer waveforms. Embodiments of the invention further advantageously can manipulate the statistics of the waveform without expanding the spectral bandwidth of the allocated channels. Embodiments of the invention can be applied to either multiple carrier or single carrier systems to constrain an output signal within predetermined peak to average bounds. Advantageously, the techniques can be used to enhance the utilization of existing multicarrier RF transmitters, including those found in third generation cellular base stations. However, the peak to average power level managing techniques disclosed herein can apply to any band-limited communication system and any type of modulation. The techniques can apply to multiple signals and can apply to a wide variety of modulation schemes or combinations thereof.Type: GrantFiled: July 20, 2001Date of Patent: June 13, 2006Assignee: PMC - Sierra Inc.Inventors: Andrew S. Wright, Richard E. Ryan, Bartholomeus T. W. Klijsen, Denis John Peregrym, Brenda Davison