Abstract: The present invention is related to methods and apparatus that can advantageously reduce a peak to average signal level exhibited by single or by multicarrier multibearer waveforms. Embodiments of the invention further advantageously can manipulate the statistics of the waveform without expanding the spectral bandwidth of the allocated channels. Embodiments of the invention can be applied to either multiple carrier or single carrier systems to constrain an output signal within predetermined peak to average bounds. Advantageously, the techniques can be used to enhance the utilization of existing multicarrier RF transmitters, including those found in third generation cellular base stations. However, the peak to average power level managing techniques disclosed herein can apply to any band-limited communication system and any type of modulation. The techniques can apply to multiple signals and can apply to a wide variety of modulation schemes or combinations thereof.

Abstract: A received information signal is decoded to obtain the received information and to produce at least one feature of the received information signal. The received information signal is preliminary classified as containing a normal burst or a truncated burst based upon the at least one feature, to obtain a preliminary classification. Cyclic redundancy checking of the received information that is decoded is performed. The received information signal is then further classified as containing a normal burst or a truncated burst based upon the preliminary classification and whether the cyclic redundancy checking is valid, to obtain a further classification. The received information signal may be still further classified as containing a normal burst or a truncated burst based upon the further classification and at least one transition rule for normal bursts and truncated bursts between the received information signal and a previously received information signal.

Abstract: An equalizer is trained based on a packet, which includes a preamble segment, a header segment and a payload segment, wherein each of the segments has a symbol rate. Further, the equalizer has a number of filter taps. A training method of the equalizer includes adapting the filter taps according to the preamble segment and extracting from the header segment a symbol rate value of the payload segment. If the symbol rate value of the payload segment, which is extracted from the header segment, indicates that such symbol rate is higher than the symbol rates of the preamble and header segments, the filter taps are re-adapted according to the preamble segment, and a number of zeros are inserted into the preamble and header segments to account for the difference between the symbol rate of the payload segment and the symbol rates of the preamble and header segments.

Abstract: The equalizer of the present invention operates on input multipath signal samples, preferably at chip or sub-chip resolution, to remove or substantially cancel the effects of one or more secondary signals from the main path signal. Using predetermined path information for one or more of the secondary path signals, including magnitude, phase, and time offset relative to the main path signal, the equalizer compensates input multipath signal samples by subtracting estimated secondary signal values from the input samples. For each input sample, the equalizer forms a sliced sample, where the sliced sample represents a nominal phase value defined by the modulation scheme used in the original chip or symbol transmission that is closest in value to the actual phase of the input sample. These sliced samples are held in a running buffer and used, in combination with the predetermined path information and scaling logic, to form the estimated secondary signal values for compensating the input samples.

Abstract: A method and apparatus encodes data on a clock pulse signal by phase modulating a clock pulse signal by introducing a sinusoidal jitter modulation to the clock pulse signal to selectively introduce intentional jitter at clock pulse transitions, wherein the sinusoidal jitter has selectable jitter frequencies each having a given amplitude. This is followed by a data signal which may include additional data that has an encoded format of binary ones and zeros, such that the appearance of the binary one in the data signal causes the phase modulation of the clock pulse signal by the selection of one of the jitter frequencies of a given amplitude. The appearance of a binary zero causes the selection of another frequency of a given amplitude to thereby modulate the clock pulse signal resulting in a phase modulated clock pulse signal that includes the encoded data in the data or additional signal.

Abstract: Pseudo-noise (PN) carrier suppression up-converter and pseudo-noise image sideband rejection up-converter and down-converter circuits are provided. The image sideband rejection circuits enable the use of single step up-conversion without the need for the high Q filters associated with two-step up-conversion architectures. For carrier suppression, the frequency spectrum of an input signal is PSK (BPSK or QPSK) spread by a PN signal and the spread signal is up-converted using a PSK (BPSK or QPSK) modulated carrier (local oscillator) modulated by the same PN sequence. In an up-converter, a carrier is QPSK modulated using independent PN sequences and the frequency spectrum of the input signal is QPSK spread using the same independent PN sequences whereby image sideband rejection results upon up-converting the QPSK spread signal in a mixer using the QPSK modulated carrier.

Abstract: A data carrier adapted to receive data (D) in the form of data blocks, which data blocks include delimiter data (SD) and (ED) and useful data (UD), includes delimiter data detection means adapted to detect delimiter data (SD) and (ED) of a data block and to generate and supply at least one useful data start signal (SOF; SOFA, SOFB), in which also after the supply of the useful data start signal (SOF; SOFA) the delimiter data (SD) and (ED) can be re-detected continually and the useful data start signal (SOF; SOFB) can be generated and supplied.

Abstract: The present invention comprises a phase-locked loop which generates a first clock signal, and a phase-locked loop which generates a second clock signal. An upper limit value of a jitter transmission frequency in the phase-locked loop in which a jitter signal is transmitted to the first clock signal without being suppressed, is not less than an upper limit value of a jitter transmission frequency. An upper limit value of a jitter transmission frequency from the phase-locked loop to the phase-locked loop in which a jitter signal is transmitted to the second clock signal without being suppressed, is not more than an upper limit value of a jitter transmission frequency.

Abstract: A QAM modulation system capable of setting a number of multilevel to approximate 2(p+0.25) (p is an integer equal to or more than 3) or 2(p+q/n). An input data signal of 4p+1 bits are converted into four signals of p+1 bits, there being a predetermined relationship between the input data signal and the converted signals. The converted four signals are assigned to four phase planes, respectively. The four signals are time-division multiplexed and multilevel-modulated. Thereby, it becomes possible to set the number of multilevel to approximate 2(p+0.25).

Abstract: A search path recovery mechanism for a sequential decoder employs a prescribed self-concatenated “Loeliger” convolutional code, that is either decodable by the sequential decoder for data recovery, or is decodable (although sub-optimally) by a Viterbi decoder as an adjunct to the sequential decoder to improve statistics during path recovery. The Viterbi decoder is incorporated in an alternate decoder which includes metric calculators, that compute branch metrics, that are alternately coupled to the Viterbi decoder, operating at twice the symbol rate. Using estimate bits from the Viterbi decoder, a syndrome former estimates the recovered state and generates an estimate of the validity of the recovered state. Their validity is verified by a path recovery detector, which operates as a zero error detection filter by summing a prescribed number of previous syndrome former outputs.

Abstract: Methods and apparatus for canceling co-channel interference in a receiving system using spatio-temporal whitening. In some embodiments, a spatio-temporal interference canceling method, and apparatus for carrying out the method are provided which effectively cancel co-channel interference despite frequency offset between the desired signal and the interferer in a TDMA type system. Real and imaginary component values of the total received signal are used for virtual diversity branches, and a vector-valued auto regressive model is used to characterize the interference. In other embodiments, spatio-temporal interference whitening is used to improve timing estimates used for synchronization. The two uses of spatio-temporal whitening can be combined in one receiver. The invention is typically implemented in one or more programmed digital signal processors or application specific integrated circuits (ASICS), embodied in a receiving system.

Abstract: A device for use in a digital video receiver. The device generally comprising a demodulator circuit, a decoder circuit, a plurality of bi-directional buffers, and a circuit. The demodulator circuit may be configured to generate (i) a first clock signal compliant with a standard interface for the digital video receiver and (ii) a first plurality of data signals compliant with the standard interface. The decoder circuit may be configured to receive a second plurality of data signals compliant with the standard interface. The plurality of first bi-directional buffers may be configured to multiplex the first data signals with the second data signals at a plurality of data interfaces in response to the first clock signal. The circuit may be configured to generate a direction signal at a direction interface in response to the first clock signal to indicate a direction of the data interfaces.

Abstract: A delay-locked-loop (DLL) that has increased precision and a wide range of operation is formed by utilizing a chain of delay blocks to add or subtract a discreet amount of delay, and a voltage-controlled delay line (VCDL) to add or subtract a smaller amount of delay. The delay blocks allow the delayed clock signal to get close to the reference clock signal, while the VCDL allows the delayed clock signal to lock onto the reference clock signal.

Abstract: Error correction coding and decoding according to a serial concatenated modulation system are carried out under high code rate. A coding apparatus 1 comprises three convolutional coders 10, 30 and 50 for carrying out convolutional operation; two interleavers 20 and 40 for rearranging order of data input; and a multi-value mapping circuit 60 for carrying out mapping of a single point on the basis of a predetermined modulation system. The coding apparatus 1 carries out convolutional operation whose code rate is “?” as coding of extrinsic codes by a convolutional coder 10, and carries out convolutional operation whose code rate is “1” as coding of inner codes by a convolutional coder 50, and a multi-value modulation mapping circuit 60 applies mapping to a transmission symbol of a 8 PSK modulation system to output it as a single code transmission symbol.

Abstract: The repetitive structure of a preamble signal is exploited to enhance timing synchronization performance and frame start detection performance under adverse channel conditions. Received values are cross-correlated in time against a known noise-free version of the preamble. The presence of peaks in the cross-correlation output indicates presence of a frame. The peak locations provide symbol timing. Further cross-correlation processing and/or non-linear processing can be used to enhance the signal to noise ratio of the peaks.

Abstract: A CAN communication line is operated whilst detecting a ground level shift on the communication line through storing a data element indicative for the shift. In particular, a current line voltage level is compared to a standard level, and a thresholded version of the comparison is fed to a storage element that is triggered by a local transmission indicator signal. Then a ground shift sample bit from the storage element is outputted.

Abstract: A system and method for providing optimum wireless communication spreading code selection such that communication channel interpath interference is minimized. In Direct-Sequence Spread-Spectrum, the autocorrelation properties of a spreading code greatly affects the inherent ability of a system to resist multipath. Low/spreading gain codes (or “short” codes) associated with high data rates do not perform well where large-amplitude multipath is present. The system and method presented herein overcomes this problem by selecting spreading codes in such a way that interference caused by multipath is minimized. The system and method does so by determining the characteristics of the radio-frequency link in order to select a spreading code that will minimize interpath interference.

Abstract: The present digital synchronous circuit includes a clock generating circuit for outputting a plurality of clock signals CLK1 to CLKn, a plurality of first latch circuits, each for receiving an input data signal DIN at a data input terminal and for receiving a corresponding clock signal at a clock input terminal, a plurality of second latch circuits, each for latching, in response to the receipt of a control signal LC, an output signal from a corresponding first latch circuit, and a control circuit for receiving input data signal DIN to generate control signal LC. Control circuit outputs control signal LC after a delay of a prescribed period of time after the change in input data signal DIN. As a result, the adverse influence of the meta-stable state that occurs when sampling an asynchronous input data signal DIN is avoided, while at the same time, the chip size and power consumption are limited.

Abstract: A device for modulating a carrier signal simultaneously performs frequency translation, upsampling, and pulse shaping. The device includes a mapper generating a first data signal. A complex mixer and an upsampling device are used to increase the data value frequency and spectrum shift the data signal. A finite impulse response filter operating on the data signal generates a digital signal representing the modulated carrier.

Abstract: A balanced peak detector circuit adjusts differential voltage signals. In one embodiment, the peak detector uses competing current paths to provide a charging current to a storage capacitor. The charge on the storage capacitor is used to adjust either a transconductance or a transimpedance circuit. An offset current can be used to adjust the charge stored on the capacitor to change a peak-to-peak output voltage from the transimpedance circuit. In one embodiment, the offset current can be adjusted using an adjustable current source. A discharge circuit has been describe that allows a discharge of the capacitor to be controlled.