Abstract: A method and apparatus are disclosed for deinterleaving expanded interleaved data blocks, particularly for use in a wireless telecommunications system such as provided by the Third Generation Partnership Project (3G) standard. The data is processed on a sequential element basis where each element has a pre-determined number of bits M which bits are contained in a block of sequential data words W?. The elements are extracted from the block of words W? in sequential order, each element being extracted from either a single or two sequential interleaved words within the set of words W?. The elements are stored in selective location within a set of words W of a deinterleaver memory such that upon completion of the extraction and writing of all the elements, the words W from the deinterleaver memory can be sequentially read out to correspond to an original data block of bits from which the block of interleaved elements was created.

Abstract: An apparatus and method for eliminating a vestigial sideband (VSB) pilot tone in a vestigial sideband/quadrature amplitude modulation (VSB/QAM) receiving system, is provided. This apparatus eliminates a vestigial sideband (VSB) pilot tone in a vestigial sideband/quadrature amplitude modulation (VSB/QAM) shared receiving system including a VSB/QAM shared modulator for demodulating a received VSB signal and outputting I-axis VSB symbols and Q-axis VSB symbols.

Abstract: Methods and apparatus are provided for implementing a receiver capable of receiving signals in simultaneous bi-directional current mode differential links. The receiver comprises a resistor-summing network and a differential amplifier. The resistor-summing network can also comprise capacitors for the purpose of attenuating high-frequency noise at the differential amplifier. The high-frequency noise can arise from impedance discontinuities in the signal paths or from differences in rising or falling transition times between the data driver and the replica driver in the links.

Abstract: A wireless communication network comprising a wireless receiver. The wireless receiver comprises at least a first antenna for receiving packets, wherein each of the received packets comprises a plurality of bits and each of the plurality of bits is modulated by a frequency offset. The wireless receiver also comprises circuitry for cycling through a hopping sequence, wherein the hopping sequence comprises a sequence of frequency bands and circuitry for demodulating each received packet in response to a frequency band in the hopping sequence. The wireless receiver also comprises circuitry for detecting the frequency offset of each of the plurality of bits and converting the frequency offset of each of the plurality of bits into a corresponding DC voltage for each of the plurality of bits.

Abstract: The present invention provides a phase locked loop circuit comprising: a frequency divider for frequency-diving an output signal to generate frequency-divided pulses; an oscillator for generating the output signal under control to an oscillation frequency by a control voltage obtained from a signal corresponding to a phase difference between the frequency-divided pulses and a reference frequency signal; and a controller for performing such a control that plural kinds of frequency dividing rate are switched to be given to the frequency divider for every time period having a predetermined number of the frequency divided pulses, and at a boundary of switching the plural kinds of frequency dividing rate, the plural kinds of frequency dividing rate are given co-existentially to the frequency divider, and further for switching the coexistent plural kinds of the frequency-dividing rate, the next frequency dividing rate is given before a first appearance of a frequency peak in a transitional characteristic of the fre

Abstract: Adaptive antenna array techniques for use in an orthogonal frequency division multiplexed spread-spectrum multi-access (OFDM-SSMA) cellular wireless system or other type of wireless communication system. A base station of the system includes an antenna array and a base station receiver. The base station receiver implements an adaptive antenna gain algorithm which estimates a spatial covariance matrix for each of K mobile stations communicating with the base station. The spatial covariance matrix for a given one of the mobile stations is determined at least in part based on a unique hopping sequence of the mobile station, and provides a correlation between signals received from the mobile station at different antenna elements within the antenna array. An average spatial covariance matrix for a set of received signals is also generated.

Abstract: A signal delay circuit that compensates for other delays introduced within the signal delay circuit itself. A delay-locked loop may produce multiple delayed clock signals, each having a defined phase difference with respect to, and representing a different delay from, a reference clock. A synchronization circuit may determine a first selection value that selects a first delayed clock whose delay compensates for the propagation delays created in a selection circuit. A selection circuit may add a specified offset value to the first selection value to produce a second selection value, and use the second selection value to select a second delayed clock whose delay approximates the sum of the internal delay of the selection circuit and the delay specified by the offset value.

Abstract: In a communication system in which an incoming signal is pulse shaped prior to detecting the information bearing point of the signal, processing overhead can be significantly reduced by only processing the sample points corresponding to the information bearing point and two points bounding the information bearing point. During signal acquisition, the signal is over sampled and the pulse shaping filter processes every sample point, or every Nth sample point in the case of down sampling. Once the sample point corresponding to the information bearing point is determined, the pulse shaping filter can be instructed to only process the sampling corresponding to the information bearing point and two neighboring samples. The system and method is adaptive, in that the samples that are processed can shift as the information bearing point shifts relative to the sample points. This is accomplished by re-synchronizing the timing of the received slot.

Abstract: A method for maintaining synchronization between a transmitter and a receiver is disclosed. The method offsets time drift which causes a degradation in the quality of communication between a transmitter and a receiver. The method comprises using a first sampling time to obtain a first sequence of hard decision symbols for decoding contents of a portion of a received packet, switching to a second sampling time upon degradation in a reliability of the symbols, and using the second sampling time to obtain a second sequence of hard decision symbols for decoding contents of a remaining portion of the received packet.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: An over-the-air (OTA) re-programming method of a radio transceiver to make the transceiver compliant with arbitrary one of a plurality of networks. According to the method, a pilot channel for dedicated use and a bootstrap channel having a bandwidth enough to download the re-programming data are provided. The bandwidth of the pilot channel is narrower than the bandwidth of the bootstrap channel. First, at least frequency and radio access parameters of the bootstrap channel are broadcasted on the pilot channel and then the re-programming data to the radio transceiver is downloaded on the second channel based on the broadcasted parameters.

Abstract: A system and a method for switching antenna fields without waiting until data packets containing errors are detected. This is accomplished by monitoring the signal power for each antenna field immediately after receipt of data packets via the currently active antenna field and then switching to another antenna field having greater signal power. A communications channel is provided which has a capacity greater than that required by the data to be transmitted. This extra capacity is used to introduce time periods when no data is being transmitted. During these time periods, known bit patterns are transmitted, and the signal power during receipt of each of these blank packets is estimated for each antenna field. The receiver then switches to the most appropriate antenna field based on highest signal power (e.g., based on a weighted average for the N-th most recent sample periods) and continues to receive the transmitted data without interruption.

Abstract: A transmitter of a wireless modem may be ramped up with quicker ramp up times and better splatter control by using software controllable ramp up techniques. A digital data signal source sends data to digital-to-analog converters used to generate a ramp with the desired duration and shape for maximum gain with minimum splatter. A transmitter digital-to-analog converter is sent constant I/Q data to bias the input of the I/Q modulator to maximum gain when combined with a direct current voltage. A controller digital-to-analog converter is sent incremented ramp data to shape the ramp and provide maximum gain at the output of the I/Q modulator.

Abstract: A signal synchronization mapper for mapping an input data stream characterized by a first frequency (typically a SONET/SDH stream) into an output data stream characterized by a second frequency. A phase lock control loop containing a “delta-sigma” (&Dgr;-&Sgr;) modulator which functions as a voltage controller oscillator synchronizes the data rate of the output stream to that of the input stream in a manner which simplifies attenuation of jitter energy when the output data stream is desynchronized (demapped). The modulator generates an accurate pulse train by duty-cycle dithered modulation of the input stream, which the mapper interprets as stuff/nullide-stuff commands such that the mapping operation is lossless over time (i.e. the number of bits in equals the number of bits out over time) thus allowing utilization of a FIFO buffer without the need to monitor the buffer's depth or its pointers.

Abstract: The prior art teachings for encoding signals and transmitting them over a plurality of antennas are advanced by disclosing a method for encoding for any number of transmitting antennas.

Abstract: The present invention is directed to a system and method for reducing the need to perform signal clipping in a DMT transmitter. In accordance with one aspect of the invention, a method performs an inverse Fourier Transform on the input to produce a time-domain, digital value to be transmitted to a remote receiver. The method then evaluates the magnitude of the digital value to determine whether the magnitude exceeds a threshold value. Then, the method alters the input and re-performs an inverse Fourier Transform on the altered input, only if the step of evaluating the magnitude determines that the magnitude of the digital value exceeds the threshold value.

Abstract: Method and apparatus for transmitting encoded signals with increased data speed in communications system using system clock synchronization and bit robbing techniques to attain high transmission rates is provided.

Abstract: An apparatus for and method of generating a signal for equalizing propagation delay among parts of a transceiver are disclosed. The parts each have a plurality of channels, and each channel is configured to receive the signal. The apparatus includes a master circuit and a dummy channel circuit. The master circuit is configured to receive and lock to a reference clock signal, and in accordance therewith generate a reference delay signal and an adjusted clock signal. The dummy channel circuit is configured to receive the adjusted clock signal, the reference delay signal and a dummy data signal, and in accordance therewith generate an intermediate data signal, the dummy data signal and one or more control signals. The control signals correspond to a delay between the adjusted clock signal and the intermediate data signal. In this manner a uniform delay may be provided to all parts and channels.

Abstract: An equalizer based symbol timing loop system incorporates existing receiver architecture to modify an input sample stream to match a transmitter's symbol rate. The system includes a phase detector that identifies a center tap in a linear equalizer in the receiver and then captures the value of the center tap at the beginning and end of a measurement period. The phase detector then multiples the captured value of the center tap at the end of the measurement period by the conjugate of the captured center tap value at the beginning of the measurement period. The phase detector then takes the arc tangent of the multiplication result. A loop filter coupled to the phase detector multiples the arc tangent result by a scalar and adds the result to a frequency difference estimate. A coefficient generator then determines the interpolation phase for an input sample stream based on the frequency difference estimate and generates interpolator coefficients based on the interpolation phase.

Abstract: A method for processing received voice data in a voice data processing system including a receiving buffer.