Patents Examined by Khanh V. Nguyen
  • Patent number: 10666211
    Abstract: A power amplifier circuit includes a bias circuit and an amplifier circuit. The bias circuit includes a first bias circuit to receive a reference voltage and an operation voltage and generate a first bias signal, a bias supply circuit to transmit the base bias signal to a base of a power amplifier, based on the first bias signal input from the first bias circuit, a switching control circuit to transmit a switching signal after a preset delay time based on a driving start signal, and a switching circuit connected between an output node of the first bias circuit and a ground, to operate in an ON state after the delay time in response to the switching signal to form a current path between the output node of the first bias circuit and the ground.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: May 26, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Bo Hyun Hwang, Dae Hee No, Jun Goo Won, Ki Joong Kim, Sung Hwan Park, Da Hye Park
  • Patent number: 10666214
    Abstract: An apparatus includes an amplifier and a gain control circuit. The amplifier may be configured to provide multiple gain steps. The gain control circuit may be configured to provide fast and precise changes between the multiple gain steps of the amplifier. The gain control circuit may be further configured to change an impedance of the amplifier to switch between the gain steps. The gain control circuit may be further configured to compensate for changes in frequency response related to changing the impedance. The gain control circuit may be further configured to inject a complementary charge to an input of the amplifier to correct a bias voltage deviation and a transient caused by the gain control circuit.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: May 26, 2020
    Assignee: Integrated Device Technology, Inc.
    Inventors: Victor Korol, Roberto Aparicio Joo
  • Patent number: 10666212
    Abstract: A positive-side power supply terminal (1-1a) of a differential amplifier (1-1) is connected to a positive-side power supply line (L1). A negative-side power supply terminal (1-2b) of a differential amplifier (1-2) is connected to a negative-side power supply line (L2). A negative-side power supply terminal (1-1b) of the differential amplifier (1-1) and a positive-side power supply terminal (1-2a) of the differential amplifier (1-2) are connected to each other. A final-stage amplifier (2) is connected between the positive-side power supply line (L1) and the negative-side power supply line (L2).
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: May 26, 2020
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka
  • Patent number: 10666201
    Abstract: A power amplifier module includes a first power amplifier circuit configured to output a first amplified signal obtained by amplifying an input signal; a second power amplifier circuit configured to output a second amplified signal obtained by amplifying the first amplified signal; and a matching network connected between the first power amplifier circuit and the second power amplifier circuit. The matching network includes a first capacitor connected in series between the first power amplifier circuit and the second power amplifier circuit, a second capacitor connected in series between the first capacitor and the second power amplifier circuit, a first inductor connected between a point between the first capacitor and the second capacitor and a ground, and a second inductor connected in series between the first power amplifier circuit and the first capacitor.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: May 26, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hisanori Namie, Satoshi Goto, Satoshi Tanaka
  • Patent number: 10666200
    Abstract: Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal, a power management circuit that controls a voltage level of a supply voltage of the power amplifier, and a bias control circuit that biases the power amplifier. The power management circuit is operable in multiple supply control modes, such as an average power tracking (APT) mode and an envelope tracking (ET) mode. The bias control circuit is configured to switch a bias of the power amplifier based on the supply control mode of the power management circuit.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Netsanet Gebeyehu, Srivatsan Jayaraman, Edward James Anthony
  • Patent number: 10666210
    Abstract: A power tube driver of a class-D audio amplifier includes high-side and low-side fixed charge/discharge gate driving circuits, high-side and low-side power tubes, a dead time generation circuit based on gate voltage detection, high-side and low-side gate charge/discharge accelerating circuits, and high-side and low-side gate voltage detection circuits. The class-D audio amplifier with the features of low radiation interference, and high efficiency, linearity and robustness can be balanced easily.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 26, 2020
    Assignee: SI EN TECHNOLOGY (XIAMEN) LIMITED
    Inventor: Chunhui Ye
  • Patent number: 10659887
    Abstract: A system may include a charge pump configured to transfer electrical energy from a source of electrical energy coupled to an input of the charge pump to an energy storage device coupled to an output of the charge pump and configured to store the electrical energy transferred from the source of electrical energy, a power converter configured to transfer electrical energy from the energy storage device to an output of the power converter, wherein the power converter comprises a first plurality of switches and a power inductor arranged such that one switch of the first plurality of switches is coupled between the power inductor and the output of the charge pump, an output stage configured to transfer electrical energy between the output of the power converter to a load coupled to an output of the output stage, the output stage comprising a second plurality of switches, and a controller configured to generate an output voltage at the output of the output stage as an amplified version of an input signal.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: May 19, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric J. King, Christian Larsen, Anthony S. Doy
  • Patent number: 10658982
    Abstract: Apparatus and method for dynamically linearizing multi-carrier power amplifiers. In one example, the method includes storing a correction set including a plurality of correction solutions and loading the correction set into an RF power amplifier linearizer. The method includes determining a first carrier configuration of an RF transmitter during a first timeslot of operation of the RF transmitter and sending a first correction solution index to the RF power amplifier linearizer. The first correction solution index corresponds to a first correction solution of the plurality of correction solutions. The method also includes determining that a carrier configuration change is initiated to operate the RF transmitter with a second carrier configuration during a second timeslot of operation of the RF transmitter and sending a second correction solution index to the RF power amplifier linearizer. The second correction solution index corresponds to a second correction solution of the plurality of correction solutions.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 19, 2020
    Assignee: MOTOROLA SOLUTIONS, INC.
    Inventors: Dennis M. Drees, Mitchell R. Blozinski, Rodney W. Hagen
  • Patent number: 10651812
    Abstract: Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 12, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ambarish Roy, Eric Marsan, Stephen Richard Moreschi
  • Patent number: 10651795
    Abstract: A method and a device for amplifying an input signal include a power amplifier for amplifying a binary input signal, a modulation device for generating the binary input signal on the basis of the input signal, the input signal being a complex-valued signal and the binary input signal being a real-valued signal, the modulation device including an adding device configured to add the complex-valued input signal to a complex-valued carrier signal of a predefined frequency and to thus generate a resulting complex-valued signal, and the modulation device including a combination device connected downstream from the adding device and configured to generate the real-valued binary input signal from the real part and the imaginary part of the resulting complex-valued signal by combining the real part and the imaginary part of the resulting complex-valued signal.
    Type: Grant
    Filed: September 20, 2017
    Date of Patent: May 12, 2020
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Hung-Anh Nguyen, Wilhelm Keusgen
  • Patent number: 10651806
    Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 12, 2020
    Assignee: MAXLINEAR, INC.
    Inventors: Abhishek Jajoo, Vamsi Paidi
  • Patent number: 10651801
    Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 12, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Lei Zhu, Xin Zhao, John L. Melanson
  • Patent number: 10651809
    Abstract: An apparatus for controlling the gain and phase of an input signal input to a power amplifier comprises a gain control loop configured to control the gain of the input signal based on power levels of the input signal and an amplified signal output by the power amplifier, to obtain a predetermined gain of the amplified signal, and a phase control loop configured to obtain an error signal related to a phase difference between a first signal derived from the input and a second signal derived from the amplified signal, and control the phase based on the error signal, to obtain a predetermined phase of the amplified signal. The phase control loop delays the first signal such that the delayed first signal and the second signal used to obtain the error signal correspond to the same part of the input signal. The apparatus may be included in a satellite.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: May 12, 2020
    Assignee: Astrium Limited
    Inventor: Martin Goss
  • Patent number: 10651803
    Abstract: Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 12, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Seung Bae Lee, Michael Edwin Butenhoff, Sudhir Nagaraj
  • Patent number: 10644662
    Abstract: A amplifier circuit in some embodiment includes a differential amplifier have a pair of current sources. Each of the current sources includes two or more current-generating transistors and respective switching transistors, which can be turned on and off by a gain input code to tune the gain of the amplifier. A common-mode controller includes a similar pair of current sources as the differential amplifier. The common mode controller receives a common-mode signal of the input signal and a common-mode gain input code, and maintains the common-mode gain of the amplifier circuit when the differential gain changes. The amplifier circuit is switchable between a buffer mode and an equalizer mode.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: May 5, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Chun Yang, Wei Chih Chen, Yu-Nan Shih
  • Patent number: 10644665
    Abstract: An amplifier includes amplification stages connected in parallel between an input point and an output point and a feedback circuit, wherein the amplification stages each include a transistor configured to amplify a signal supplied from the input point, a harmonic processing unit configured to process harmonics present in an amplified signal output from an output node of the transistor, a connection point between the output node and the harmonic processing unit, and a transmission line connecting the connection point and the output point, wherein the feedback circuit feeds back a signal at the output point or a midway point of the transmission line of a given one of the amplification stages to a first end of a resistor connected to the connection point of the given one of the amplification stages, a second end of the resistor being connected to the connection point of another one of the amplification stages.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 5, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Naoko Kurahashi, Masaru Sato
  • Patent number: 10637401
    Abstract: Provided is a current output circuit that includes: a first FET that has a power supply voltage supplied to a source thereof, that has a first voltage supplied to a gate thereof and that outputs a first current from a drain thereof; a second FET that has the power supply voltage supplied to a source thereof, that has the first voltage supplied to a gate thereof and that outputs an output current from a drain thereof; a first control circuit that controls the first voltage such that the first current comes to be at a target level; and a second control circuit that performs control such that a drain voltage of the first FET and a drain voltage of the second FET are made equal to each other.
    Type: Grant
    Filed: December 13, 2017
    Date of Patent: April 28, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yusuke Shimamune, Satoshi Tanaka, Takayuki Tsutsui, Hayato Nakamura, Kazuhito Nakai, Fuminori Morisawa
  • Patent number: 10637404
    Abstract: An amplifier apparatus (332) comprises a main linear amplifier sub-circuit (402) having a main driving signal input terminal (331) and a main amplifier output terminal (406). The apparatus also comprises an auxiliary linear amplifier sub-circuit (404) having an auxiliary driving signal input terminal (357) and an auxiliary amplifier output terminal (408). A combining network (410) is operably coupled between the main amplifier output terminal (406) and the auxiliary amplifier output terminal (408), the combining network (410) having a main-side terminal (424) and an auxiliary-side terminal (434). The main linear amplifier sub-circuit (402) is arranged to generate, when in use, a main amplified signal in response to a main driving signal applied at the main driving signal input terminal (331).
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: April 28, 2020
    Assignee: u-blox AG
    Inventor: John Haine
  • Patent number: 10637519
    Abstract: A concurrent-type multiband amplifier (or a dual-band amplifier) which amplifies multiband signals concurrently using a plurality of (N) amplifier circuits which each independently amplify signals in a plurality of (N) frequency bands. An n-th (n=any of 1 to N) amplifier circuit is provided with a circuit for blocking signals in frequency bands other than the n-th frequency band so as to amplify and output only the n-th frequency band signal. The n-th amplifier circuit is designed so as to consist of its input/output impedance matching circuit for the n-th an amplifier element at the n-th frequency band.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: April 28, 2020
    Assignee: THE UNIVERSITY OF ELECTRO-COMMUNICATIONS
    Inventors: Yoichiro Takayama, Kazuhiko Honjo, Ryo Ishikawa
  • Patent number: 10637412
    Abstract: Apparatus and methods for low noise amplifiers (LNAs) are provided herein. In certain configurations, an LNA includes a mode control circuit that operates the LNA in one of a plurality of modes including a gain mode and a bypass mode, a gain circuit electrically connected between an input terminal and an output terminal and operable to amplify a radio frequency signal received from the input terminal in the gain mode, and a bypass circuit electrically connected between the input terminal and the output terminal and operable to bypass the gain circuit in the bypass mode. The bypass circuit includes a balun that provides a first amount of compensation for a difference in phase delay between the bypass circuit and the gain circuit, and the LNA further includes a phase compensation circuit operable to provide a second amount of compensation for the difference in phase delay.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: April 28, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Perihua Ye, Engin Ibrahim Pehlivanoglu, Eric J. Marsan