Patents Examined by Khanh V. Nguyen
  • Patent number: 12224718
    Abstract: This application relates to transimpedance amplifier (TIA) apparatus, in particular to a TIA apparatus suitable for receiving data using burst mode communication. The apparatus has a transimpedance amplifier configured to generate a first voltage based on a current at an input node for an input signal. A controlled voltage source, such as a dummy TIA, generates a second voltage based on a first control current. A controller is configured to collectively control the first control current and a second control current based on an indication of input signal magnitude. The first control current controls the second voltage which may be used as a slicing level. The second control current is subtracted from the current at the input node and can provide a DC restore current.
    Type: Grant
    Filed: February 2, 2022
    Date of Patent: February 11, 2025
    Assignee: Semtech Corporation
    Inventors: Matthew George Hagman, Behzad Farzaneh
  • Patent number: 12224714
    Abstract: The present disclosure is directed to apparatus and method that extends a useful operation range of an amplifier circuit. Here a low noise amplifier may be attached to a cold end of a cooler or chiller, such as a “Stirling” cryocooler after which a chamber that encloses the cold end of the cooler and the amplifier may be assembled. Gas included in the chamber may be removed by attaching an input to a vacuum pump to a portion of the chamber. After the chamber is sealed such that a low pressure in the chamber can be maintained, the cooler may be turned on in order to chill the amplifier to temperatures that reduce noise generated internally to the amplifier or to reduce amounts of return loss associated with the amplifier. The use of a Stirling cryocooler allows for the amplifier to be cooled to very low or cryogenic temperatures.
    Type: Grant
    Filed: May 17, 2021
    Date of Patent: February 11, 2025
    Assignee: AmpliTech, Inc.
    Inventor: Fawad Maqbool
  • Patent number: 12218636
    Abstract: A Doherty amplifier according to the disclosure includes an input terminal, a first input transmission line connected to the input terminal via a branch portion, a second input transmission line connected to the input terminal via the branch portion, a carrier amplifier connected to the first input transmission line, a peak amplifier connected to the second input transmission line, a first output transmission line including one end connected to output of the carrier amplifier, a second output transmission line including one end connected to output of the peak amplifier, a synthesis line including one end connected to another end of the first output transmission line and another end of the second output transmission line and an output terminal connected to another end of the synthesis line, wherein the first output transmission line includes a wide portion which is wider than another portion of the first output transmission line.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: February 4, 2025
    Assignee: Mitsubishi Electric Corporation
    Inventor: Shohei Hatanaka
  • Patent number: 12212292
    Abstract: In certain examples, the disclosure involves or is directed to a circuit-based apparatus that has a T-network, and a plurality of circuit paths with a first path having a first switching node to respond to an RF input signal that is characterized by a first phase, and with a second path having a second switching node to respond to the RF input signal characterized by a second phase that is different than the first phase. The circuit paths may be configured as a push-pull amplification circuit. The T-network may be arranged between the first and second switching nodes and may include a variable impedance circuit. The variable impedance circuit may be adjusted, in accordance with a selected frequency of the RF input signal. The T-network may be characterized by a resonance frequency shunts a second harmonic current associated with the resonance frequency, thereby permitting for use of different selected frequencies.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: January 28, 2025
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Zikang Tong, Lei Gu, Juan Rivas-Davila
  • Patent number: 12206371
    Abstract: Example embodiments relate to power amplifier devices and semiconductor dies. One example power amplifier device includes a semiconductor die having a first input terminal and a first output terminal. The power amplifier device also includes a power transistor integrated on the semiconductor die and including a second input terminal and a second output terminal arranged at an input side and output side of the power transistor, respectively. The power transistor has an output capacitance. Further, the power amplifier device includes a shunt network that includes a plurality of first bondwires arranged in series with a first capacitor. The first capacitor is arranged near the input side of the power transistor. At one end of the shunt network one end of the plurality of first bondwires is coupled to the second output terminal. Additionally, the power amplifier includes a pair of coupled lines formed on the semiconductor die.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: January 21, 2025
    Assignee: Ampleon Netherlands B.V.
    Inventor: Josephus Henricus Bartholomeus Van Der Zanden
  • Patent number: 12199581
    Abstract: Equalizer circuitry includes a differential target voltage input, an equalizer output, a first operational amplifier, and a second operational amplifier. The differential target voltage input includes a target voltage input node and an inverted target voltage input node. The first operational amplifier and the second operational amplifier are coupled in series between the differential target voltage input and the equalizer output. The first operational amplifier is configured to receive a target voltage signal and provide an intermediate signal based on the target voltage input signal. The second operational amplifier is configured to receive the intermediate signal and an inverted target voltage signal and provide an output signal to the equalizer output.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: January 14, 2025
    Assignee: Qorvo US, Inc.
    Inventors: Nadim Khlat, Michael R. Kay, James M. Retz
  • Patent number: 12191972
    Abstract: A technology is described for a repeater. A repeater can comprise: a server port; a donor port; a first uplink (UL) amplification and filtering path coupled between the server port and the donor port, wherein the UL amplification and filtering path is configured to pass a UL signal of a first band and a UL signal of a second band through a first bandpass filter; a first downlink (DL) amplification and filtering path coupled between the server port and the donor port, wherein the first DL amplification and filtering path is configured to pass a DL signal of the first band and a DL signal of a third band through a second bandpass filter.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: January 7, 2025
    Assignee: Wilson Electronics, LLC
    Inventor: Christopher Ken Ashworth
  • Patent number: 12191831
    Abstract: An amplifying device includes a main amplifier; a first feedback circuit coupled between an input terminal of the main amplifier and an output terminal of the main amplifier; an input coupling circuit coupled between the input terminal of the main amplifier and a first node; and an amplifying feedback circuit coupled between the output terminal of the main amplifier and the first node, wherein the first feedback circuit and the amplifying feedback circuit are negative feedback circuits.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 7, 2025
    Assignee: Seoul National University R&DB Foundation
    Inventors: Junyoung Park, Suhwan Kim
  • Patent number: 12191826
    Abstract: A method of adjusting an impedance of a power amplifier of a radio frequency system for matching with an antenna switch die is disclosed. In one aspect, the method includes connecting the power amplifier to the antenna switch die via an impedance adjustment circuit, the impedance adjustment circuit including an input node, an output node, a plurality of electrical components arranged between the input node and the output node, and at least one switch configured to selectively electrically connect at least one of the electrical components to the input node and the output node. The method further includes determining an Error Vector Magnitude of the radio frequency system for each of a plurality of states of the at least one switch, and controlling the at least one switch to enter the state of the plurality of states that minimizes the Error Vector Magnitude of the radio frequency system.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: January 7, 2025
    Assignee: Skyworks Solutions, Inc.
    Inventors: William J. Domino, Craig Joseph Christmas, Joseph Anton Pusl, III, René Rodríguez
  • Patent number: 12191816
    Abstract: A complementary balanced low-noise amplifier is disclosed. In one aspect, the low-noise amplifier (LNA) may be a single-ended cascoded complementary common-source LNA that is capable of operating in low-power conditions. In particular, the LNA may include a first path with a common-source amplifier formed from an N-type material and a second path with a common-source amplifier formed from a P-type material that collectively form a complementary common-source amplifier. By providing two paths in the complementary amplifier, headroom may be preserved for output transistors. Additionally, higher-order intercept points (e.g., IP2 or IP3) characteristics have better performance profiles resulting in better overall performance and improved user experience.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: January 7, 2025
    Assignee: Qorvo US, Inc.
    Inventor: Marcus Granger-Jones
  • Patent number: 12183648
    Abstract: In a semiconductor device, when a first surface of a first member is viewed in plan, a plurality of circuit blocks are disposed in an inner region of the first surface. The second member is joined to the first surface of the first member in surface contact with the first surface. The second member includes one or more circuit blocks. A conductive protrusion protrudes from the second member on an opposite side to the first member. One of the circuit blocks in the second member constitutes a first amplifier circuit including a plurality of first transistors that are connected in parallel to each other. At least one of the circuit blocks in the first member overlaps at least one circuit block in the second member in a plan view.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: December 31, 2024
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Mikiko Fukasawa, Satoshi Goto, Shunji Yoshimi
  • Patent number: 12176857
    Abstract: This Doherty amplifier includes: a carrier amplifier for amplifying a first signal and outputting the amplified first signal; a peaking amplifier for amplifying a second signal and outputting the amplified second signal, the peaking amplifier having a non-linear output capacitance; a first output circuit for transmitting the first signal output from the carrier amplifier; a second output circuit for functioning as a virtual short stub when the peaking amplifier does not perform an amplification operation, and transmitting the second signal output from the peaking amplifier; and a combining circuit for combining the first signal transmitted by the first output circuit and the second signal transmitted by the second output circuit and outputting a combined signal of the first signal and the second signal, wherein, when the peaking amplifier performs the amplification operation, the second output circuit transforms an impedance seen by looking into the combining circuit from the peaking amplifier into an impedan
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: December 24, 2024
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuji Komatsuzaki, Satoru Honda, Shuichi Sakata, Shintaro Shinjo
  • Patent number: 12166458
    Abstract: The present disclosure provides a RF power amplifier and a method for manufacturing a Doherty power amplifier. The RF power amplifier includes at least one transistor, a harmonic termination circuit, and an impedance inverter. The harmonic termination circuit has one terminal directly connected to the drain electrode of the transistor and contributes as a part of a harmonic matching network for the transistor at the second harmonic and/or the third harmonic of the fundamental frequency. The impedance inverter is configured to perform impedance inversion of a static load or a modulated load at the fundamental frequency without affected by the harmonic termination circuit.
    Type: Grant
    Filed: October 8, 2021
    Date of Patent: December 10, 2024
    Inventor: Rachit Joshi
  • Patent number: 12166454
    Abstract: The present disclosure relates to devices and methods for detecting and preventing occurrence of a saturation state in a power amplifier. A power amplifier module can include a power amplifier including a cascode transistor pair. The cascode transistor pair can include a first transistor and a second transistor. The power amplifier module can include a current comparator configured to compare a first base current of the first transistor and a second base current of the second transistor to obtain a comparison value. The power amplifier module can include a saturation controller configured to supply a reference signal to an impedance matching network based on the comparison value. The impedance matching network can be configured to modify a load impedance of a load line in electrical communication with the power amplifier based at least in part on the reference signal.
    Type: Grant
    Filed: April 14, 2023
    Date of Patent: December 10, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: David Steven Ripley, Philip John Lehtola
  • Patent number: 12160203
    Abstract: An amplifier circuit includes an amplifier having an amplifier input and an amplifier output. The amplifier circuit includes a transformer having a primary winding in series with the amplifier output and a secondary winding coupled to the amplifier input. The primary winding and the secondary winding are arranged such that a portion of a magnetic field generated by the primary winding couples to the secondary winding through a magnetically coupled feedback loop, thereby providing feedback from the amplifier output to the amplifier input. An output load arrangement is connected to the primary winding wherein the output arrangement includes a balun. The amplifier circuit may be implemented as an integrated circuit and where the primary and secondary windings are integrated in different metal layers of the integrated circuit or are otherwise arranged to effect a desired degree of magnetic coupling and feedback from the amplifier output to the amplifier input.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: December 3, 2024
    Assignee: QuantalRF AG
    Inventors: Ali Fard, Mats Carlsson
  • Patent number: 12160202
    Abstract: An amplifying device includes a radio frequency (RF) signal input terminal to which an RF signal is input, a buffer circuit, a linearizer including a transistor, a power amplifier, and a control circuit. The control circuit outputs a first gate voltage when a level of the RF signal input is a first level, the first gate voltage causing the transistor to perform a class B operation. The control circuit outputs a second gate voltage when the level of the RF signal is a second level higher than the first level, the second gate voltage causing the transistor to perform a class AB operation. Output impedance of the buffer circuit that is seen from an input side of the linearizer is set such that a reflection loss of the RF signal input from the buffer circuit to the linearizer is a predetermined level or less.
    Type: Grant
    Filed: November 17, 2021
    Date of Patent: December 3, 2024
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventor: Koshi Hamano
  • Patent number: 12149208
    Abstract: An electronic circuit according to various embodiments may comprise: a switch circuit, wherein the switch circuit may comprise: a first switch connected to a first port and a second switch connected to a second port, the first and second switches being connected in series with each other; a first parallel switch connected to a node between the first switch and the second switch; and a first shunt inductor connected to the node between the first switch and the second switch and configured to cancel a parasitic capacitance component of the first parallel switch.
    Type: Grant
    Filed: February 11, 2020
    Date of Patent: November 19, 2024
    Assignees: Samsung Electronics Co., Ltd., Korea Advanced Institute of Science and Technology
    Inventors: Sungku Yeo, Seunghun Wang, Songcheol Hong, Jaeseok Park, Jinseok Park, Chongmin Lee
  • Patent number: 12143077
    Abstract: One aspect of this disclosure is a power amplifier module that includes a power amplifier, a semiconductor resistor, a tantalum nitride terminated through wafer via, and a conductive layer electrically connected to the power amplifier. The semiconductor resistor can include a resistive layer that includes a same material as a layer of a bipolar transistor of the power amplifier. A portion of the conductive layer can be in the tantalum nitride terminated through wafer via. The conductive layer and the power amplifier can be on opposing sides of a semiconductor substrate. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: November 12, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter J. Zampardi, Jr., Hongxiao Shao, Tin Myint Ko, Matthew Thomas Ozalas, Hong Shen, Mehran Janani, Jens Albrecht Riege, Hsiang-Chih Sun, David Steven Ripley, Philip John Lehtola
  • Patent number: 12143080
    Abstract: A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 12, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Tomokazu Kojima
  • Patent number: 12142583
    Abstract: Example embodiments relate to RF amplifier packages. One example RF amplifier package includes an input terminal, an output terminal, a substrate, a first DC blocking capacitor having a first terminal and a grounded second terminal, and a second conductor die mounted on the substrate. The semiconductor die includes a semiconductor substrate, an RE power field-effect transistor (FET) integrated on the semiconductor substrate, a gate bondbar, a first drain bondbar, a second drain bondbar, and a plurality of first bondwires connecting the second drain bondbar to the first terminal of the first DC blocking capacitor. The RF power FET includes a plurality of gate fingers that are electrically connected to the gate bondbar and that each extend from the gate bondbar towards the first drain bondbar and underneath the second drain bondbar, a first set of drain fingers, and a second set of drain fingers.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 12, 2024
    Assignee: Ampleon Netherlands B.V.
    Inventors: Josephus Henricus Bartholomeus Van der Zanden, Daniel Maassen