Patents Examined by Khanh V. Nguyen
  • Patent number: 11159132
    Abstract: The technology described in this document can be embodied in an audio power amplifier that includes a first channel and a second channel. Each of the first channel and the second channel includes an input to receive an input signal, a pair of switching devices, drive circuitry for driving the pair of switching devices to produce a signal, and an output filter to filter the signal from the pair of switching devices. The output filter is configured to provide the filtered signal to an audio load. Each of the first channel and the second channel includes a voltage feedback loop to provide a voltage of the filtered signal to a voltage controller of the audio power amplifier, and a current feedback loop to provide a current of the filtered signal to a current controller of the audio power amplifier. The audio power amplifier includes a summer for combining the input of the first channel and the input of the second channel when an output of the first channel is connected to an output of the second channel.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: October 26, 2021
    Assignee: Bose Corporation
    Inventor: Zoran Coric
  • Patent number: 11152892
    Abstract: A method and a system of calibrating a DC offset voltage on a resistor load are provided. The system may include a first operational amplifier, a second operational amplifier, a comparator, a digital signal processor, and a digital to analog convertor. At a calibration mode, under control of the digital signal processor, the system may utilize open-loop high gain characteristics of the first operational amplifier and the comparator to automatically detect and calibrate the DC offset voltage. At an operation mode, the system may automatically compensate the DC offset voltage based on the calibration of the DC offset voltage. In this way, the system and the method can automatically detect, calibrate, and compensate the DC offset voltage with reduced cost and technical complexity.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: October 19, 2021
    Assignee: Beken Corp Shenzhen
    Inventors: Desheng Hu, Donghui Gao, Jiazhou Liu, Dawei Guo
  • Patent number: 11152895
    Abstract: A Doherty amplifier is disclosed with a main amplifier having a main input in communication with a radio frequency (RF) signal input and a main output in communication with a RF signal output. Also included is a peaking amplifier having a peak input in communication with the RF signal input and a peak output in communication with the RF signal input. Further included is main neutralization circuitry having a main neutralization input in communication with the peak input and a main neutralization output in communication with the main input, wherein the main neutralization circuitry is configured to inject a main neutralization signal into the main input such that the main neutralization signal is 180°±10% out of phase and equal in amplitude to within ±10% of a main parasitic feedback signal passed from the main output to the main input by way of a main parasitic feedback capacitance.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Baker Scott, George Maxim, Dirk Robert Walter Leipold
  • Patent number: 11152893
    Abstract: A power amplifying circuit includes a first amplifying unit that amplifies a first radio-frequency signal and a second amplifying unit that amplifies a second radio-frequency signal. The first amplifying unit includes a first matching circuit that performs impedance matching for a circuit in a preceding stage, and a first amplifying circuit that amplifies the first radio-frequency signal that has passed through the first matching circuit. The second amplifying unit includes a second matching circuit that performs impedance matching for the circuit in the preceding stage, a resistor including a first end and a second end, the first end being electrically connected to the second matching circuit, and a second amplifying circuit that is electrically connected to the second end of the resistor and that amplifies the second radio-frequency signal that has passed through the resistor.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: October 19, 2021
    Assignee: MURATA MANUFACTURING CO. , LTD.
    Inventors: Takashi Yamada, Toshikazu Terashima, Yuuki Oomae
  • Patent number: 11139780
    Abstract: An envelope tracking (ET) apparatus is provided. The ET apparatus includes an amplifier array(s) configured to amplify a radio frequency (RF) signal(s) based on an ET voltage(s). The ET apparatus also includes a distributed voltage amplifier (DVA) circuit(s), which may be co-located with the amplifier array(s) to help reduce trace inductance between the DVA circuit(s) and the amplifier array(s), configured to generate the ET voltage(s) based on an ET target voltage(s). The ET apparatus further includes a signal processing circuit configured to receive an analog signal(s) corresponding to the RF signal(s) and generates the ET target voltage(s) based on the analog signal. By employing a single signal processing circuit to generate the ET target voltage(s) for the amplifier array(s), it may be possible to reduce a footprint of the ET apparatus without compromising efficiency and/or increasing heat dissipation of the amplifier array(s).
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: October 5, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11133787
    Abstract: Methods and apparatus to determine automated gain control parameters for an automated gain control protocol are disclosed. An example apparatus includes a first tuner to amplify an audio signal. Disclosed example apparatus also include a second tuner to amplify the audio signal. Disclosed example apparatus also include a first controller to tune the first tuner to apply a first gain representative of a first range of gains to the audio signal to determine a first amplified audio signal and tune the second tuner to apply a second gain representative a second range of gains to the audio signal to determine a second amplified audio signal, the second range of gains lower than the first range of gains. Disclosed example apparatus also include a second controller to select the first range of gains to be utilized in an automated gain control protocol when the first gain results in clipping of the first amplified audio signal and the second gain does not result in clipping of the second amplified audio signal.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: September 28, 2021
    Assignee: The Nielsen Company (US), LLC
    Inventors: John T. Livoti, Rajakumar Madhanganesh, Stanley Wellington Woodruff, Ryan C. Lehing, Charles Clinton Conklin
  • Patent number: 11128262
    Abstract: A number of low voltage vacuum tube circuits include using supply voltages well below the manufacturer's recommended voltages applied to the plate or screen grid. Some of the tube circuits operate at near zero plate and or screen grid voltages. Other low voltage circuits have forward biasing on one or more grids that are normally biased at a non positive voltage or a grid that is normally connected a cathode. Substantially lower supply voltages allow for example, the filament supply to also supply voltage to the plate and or grid for providing an output signal at a grid and or a plate. Also one or more voltage controlled resistors circuits are shown that include near zero plate (e.g., supply) voltage.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: September 21, 2021
    Inventor: Ronald Quan
  • Patent number: 11128264
    Abstract: A bias compensation circuit, coupled to an amplifying transistor, is disclosed. The bias compensation circuit comprises a voltage locking circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a third terminal the amplifying transistor, and the second terminal is coupled to a control terminal of the amplifying transistor; and a first resistor, coupled to the first terminal of the voltage locking circuit; wherein when the voltage locking circuit is conducted, a voltage difference between the first terminal and the second terminal is substantially constant.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: September 21, 2021
    Assignee: WIN Semiconductors Corp.
    Inventors: Po-Kie Tseng, Chih-Wen Huang, Jui-Chieh Chiu, Shao-Cheng Hsiao
  • Patent number: 11128261
    Abstract: Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can have a varying supply voltage. According to one aspect, the gate of the input transistor of the amplifier is biased with a fixed voltage whereas the gates of the other transistors of the amplifier are biased with variable voltages that are linear functions of the varying supply voltage. According to another aspect, the linear functions are such that the variable voltages coincide with the fixed voltage at a value of the varying supply voltage for which the input transistor is at the edge of triode. According to another aspect, biasing of the stacked transistors is such that, while the supply voltage varies, the drain-to-source voltage of the input transistor is maintained to a fixed value whereas the drain-to-source voltages of all other transistors are equal to one another.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 21, 2021
    Assignee: pSemi Corporation
    Inventors: Tero Tapio Ranta, Christopher C. Murphy, Jeffrey A. Dykstra
  • Patent number: 11121676
    Abstract: The present document discloses circuits and methods for providing an output voltage at an output port. In one of the embodiments, a circuit has a power amplifier having an output. In particular, the circuit may have a first transformer including a first coil and a second coil. Moreover, the circuit may have a first capacitor connected in parallel to the first coil and a second capacitor connected in parallel to the second coil. More particularly, the circuit may be adapted to have a first end of the first coil connected to the output of the power amplifier, and a second end of the first coil connected to the output port of the circuit.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: September 14, 2021
    Assignee: Dialog Semiconductor B.V.
    Inventor: Ao Ba
  • Patent number: 11121678
    Abstract: A vacuum tube amplification system includes: a first power circuit electrically connected to utility power alternating voltage to transform it into a first DC voltage; a first vacuum tube amplification load circuit having a first grounding end, the first vacuum tube amplification load circuit using the first DC voltage as operating voltage; a second power circuit electrically connected to the utility power alternating voltage to transform it into a second DC voltage and output the second DC voltage; and a second vacuum tube amplification load circuit having a second grounding end, the second vacuum tube amplification load circuit using the second DC voltage as operating voltage. The first grounding end is not directly electrically connected to the second grounding end, the first grounding end and the second grounding end are each electrically connected to a compliance ground of the utility power alternating voltage through a jumper-wire zero-ohm resistor.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: September 14, 2021
    Assignee: ECHOWELL ELECTRONIC CO., LTD
    Inventor: Hsi-Hsien Chen
  • Patent number: 11121679
    Abstract: An amplifying apparatus is provided. The amplifying apparatus comprises an amplifying circuit comprising a power amplifier and a bias circuit, the bias circuit is configured to detect an ambient temperature of the power amplifier to output a temperature voltage and regulate an internal current based on an input control signal to supply a bias current obtained by the regulation to the power amplifier; and a temperature control circuit that generates the control signal based on the temperature voltage during initial driving from a transmission mode starting point in time to an input point in time at which an input signal is input and outputting the control signal to the amplifying circuit.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Wong Jang, Byeong Hak Jo, Jeong Hoon Kim, Jong Ok Ha, Hyun Paek, Shinichi Iizuka
  • Patent number: 11121688
    Abstract: An amplifier includes a first input transistor, a second input transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal. The first current mirror circuit is coupled to the first input transistor and the second input transistor. The second current mirror circuit is coupled to the first input transistor, the second input transistor, and the first current mirror circuit.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: September 14, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ravpreet Singh
  • Patent number: 11121690
    Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (?) from the output signal and the input signal. In various embodiments the extent to which the error signal (?) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: September 14, 2021
    Assignee: Cirrus Logic, Inc.
    Inventors: John Paul Lesso, Toru Ido
  • Patent number: 11114984
    Abstract: An audio device for reducing pop noise is adapted to compensate for a direct current (DC) offset of an audio source signal and output the audio source signal to an audio playing device. The audio device includes a linear operation circuit, an adder, a digital-to-analog circuit, and an amplification circuit. The digital-to-analog circuit is coupled between the adder and the amplification circuit. The linear operation circuit generates a DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant. The adder is configured to process an input signal and the DC offset value to generate a calibration signal. The digital-to-analog circuit is configured to convert a calibration signal in a digital form to a calibration signal in an analog form. The amplification circuit is configured to process the calibration signal in the analog form to output the audio source signal.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shih-Hsin Lin, Che-Hung Lin, Yi-Chang Tu
  • Patent number: 11114396
    Abstract: In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Cree, Inc.
    Inventors: Lei Zhao, Mario Bokatius
  • Patent number: 11108363
    Abstract: An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 31, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11108360
    Abstract: A Doherty amplifier system is disclosed. The Doherty amplifier system includes a carrier amplifier having a main input for receiving a first portion of a radio frequency (RF) signal and a main output in communication with a RF signal output. A peaking amplifier has a peak input for receiving a second portion of the RF signal and a peak output in communication with the RF signal output. Further included is a first impedance inverter coupled between the main output and the peak output. A second impedance inverter is coupled between the peak output and the RF signal output. A first impedance inverter coefficient of the first impedance inverter is numerically within ±10% of a second impedance inverter coefficient of the second impedance inverter.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: August 31, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11108361
    Abstract: A multiple-path amplifier (e.g., a Doherty amplifier) includes first and second amplifier input terminals and an amplifier output terminal integrally-formed with a semiconductor die, and at least two amplifier cells positioned adjacent to each other between the amplifier input terminals and the amplifier output terminal. Each amplifier cell includes first and second transistors (e.g., field effect transistors) integrally-formed with the semiconductor die, where the first and second transistors each include a transistor input (e.g., a gate terminal) and a transistor output (e.g., a drain terminal). The first transistor input is coupled to the first amplifier input terminal, and the second transistor input is coupled to the second amplifier input terminal. A combining node is coupled to the second transistor output and to the amplifier output terminal, and a first phase shift element (e.g., an inductor) is electrically connected between the first transistor output and the combining node.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 31, 2021
    Assignee: NXP USA, Inc.
    Inventors: Ibrahim Khalil, Hussain Hasanali Ladhani, Humayun Kabir
  • Patent number: 11095258
    Abstract: A second main electrode of a first transistor is connected to a first main electrode of a sixth transistor, a second main electrode of the sixth transistor is connected to a first main electrode of a fifth transistor at a first node, a second main electrode of the fifth transistor is connected to a second main electrode of a second transistor, a control electrode of the fifth transistor is connected to the second main electrode of the fifth transistor, a second main electrode of a third transistor is connected to a first main electrode of a fourth transistor at a second node, and a control electrode of the fourth transistor is connected to the control electrode of the fifth transistor. A gain control amplifier controls a voltage supplied to a control electrode of the sixth transistor such that the first node and the second node are equal in voltage.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: August 17, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Takayuki Nakai