Patents Examined by Khanh V. Nguyen
  • Patent number: 11563410
    Abstract: A power amplification circuit can include an input impedance matching circuit associated with one or more frequency bands of a plurality of frequency bands. The power amplification circuit can include a transistor with respective input coupled to an output of the input impedance matching circuit. The power amplification circuit can include a plurality of output impedance matching circuits. Each output impedance matching circuit can be associated with a respective frequency band of the plurality of frequency bands. The power amplification circuit can include a single pole multi-throw (SPMT) switch having an input terminal connected to an output of the transistor and a plurality of output terminals. Each output terminal of the SPMT switch can be connected to a corresponding output impedance matching circuit of the plurality of output impedance matching circuits.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 24, 2023
    Assignee: Rockwell Collins, Inc.
    Inventor: Chenggang Xie
  • Patent number: 11558019
    Abstract: Disclosed is an amplifying circuit and method. In one embodiment, an amplifying circuit, includes: a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein source terminal and body terminal of the first transistor is coupled together through a first resistor.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: January 17, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Garming Liang, Simon Chai, Tzu-Jin Yeh, En-Hsiang Yeh, Wen-Sheng Chen
  • Patent number: 11552609
    Abstract: The present disclosure relates to amplifier circuitry (300) that includes a linear amplifier stage (110) that receives an input signal and outputs a first drive signal to an output node (302) and a switching amplifier stage (130) operable to output a second drive signal to the output node (302). A controller (340) is selectively operable in a first dual-amplifier mode, in which switching of the switching amplifier stage is controlled based on a current of the first drive signal, such that the current of the first drive signal does not exceed a first current threshold magnitude; and at least one other mode, in which the controller controls the switching amplifier stage such that the current of the first drive signal may exceed the first current threshold magnitude. The controller (340) selectively controls the mode of operation based on an indication (SSL) of signal level of the output signal.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 10, 2023
    Assignee: Cirrus Logic, Inc.
    Inventor: John P. Lesso
  • Patent number: 11545951
    Abstract: A system may include a first input for receiving a first signal for driving an amplifier that drives a load, a second input for receiving a second signal driven by the amplifier, and an instability detector for detecting instability of a feedback loop for controlling the first signal based on comparison of the first signal and the second signal.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: January 3, 2023
    Assignee: Cirrus Logic, Inc.
    Inventor: Dana J. Taipale
  • Patent number: 11539337
    Abstract: An amplifier includes a first input transistor, a second input transistor, a first cascode transistor, a second cascode transistor, a first current mirror circuit, and a second current mirror circuit. The first input transistor is coupled to a first input terminal. The second input transistor is coupled to a second input terminal and the first input transistor. The first cascode transistor is coupled to the first input transistor. The second cascode transistor is coupled to the second input transistor and the first cascode transistor. The first current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the first input terminal. The second current mirror circuit is coupled to the first cascode transistor, the second cascode transistor, and the second input terminal.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: December 27, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Ravpreet Singh
  • Patent number: 11539333
    Abstract: An RF transceiver front end includes a receiver limb including a length of transmission line, an impedance matching network, a downstream shunt switch and a downstream further receiver component and a transmitter limb. The impedance matching network is configured to transform the input impedance of the further receiver component to match the input impedance of the receiver limb when the shunt switch is open and the RF transceiver front end is operable in receiver mode. The impedance matching network is further configured to transform the input impedance of the shunt switch to present an open circuit as the input impedance of the receiver limb when the shunt switch is closed and the RF transceiver front end is operable in transmitter mode. The length of transmission line can be from zero to less than ?/4 at the operating frequency of the RF transceiver.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: December 27, 2022
    Assignee: NXP B.V.
    Inventors: Xin Yang, Dominicus Martinus Wilhelmus Leenaerts
  • Patent number: 11539330
    Abstract: An envelope tracking (ET) integrated circuit (ETIC) supporting multiple types of power amplifiers. The ETIC includes a pair of tracker circuits configured to generate a pair of low-frequency currents at a pair of output nodes, respectively. The ETIC also includes a pair of ET voltage circuits configured to generate a pair of ET voltages at the output nodes, respectively. In various embodiments disclosed herein, the ETIC can be configured to generate the low-frequency currents independent of what type of power amplifier is coupled to the output nodes. Concurrently, the ETIC can also generate the ET voltages in accordance with the type of power amplifier coupled to the output nodes. As such, it is possible to support multiple types of power amplifiers based on a single ETIC, thus helping to reduce footprint, power consumption, and heat dissipation in an electronic device employing the ETIC and the multiple types of power amplifiers.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: December 27, 2022
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11533034
    Abstract: An apparatus includes a controller that controls operation of an amplifier. The amplifier receives a sample voltage produced by a resistive path; the sample voltage from the resistive path is indicative of a magnitude of current through a motor winding. The controller selects a gain setting to apply to the amplifier based on one or more conditions. The selected gain setting is selected amongst multiple possible gain settings. Subsequent to selection, via application of the selected gain setting to the amplifier, and based on an output of the amplifier, the controller monitors a magnitude of the current through the motor winding. According to one configuration, the amplifier adjusts the magnitude of the selected gain setting depending on one or more parameters such as the magnitude of the current through the motor winding, a selected operational range of controlling current through the motor winding, etc.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: December 20, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Tao Zhao, Pablo Yelamos Ruiz
  • Patent number: 11533026
    Abstract: An amplifier module that implements two or more amplifying units connected in series is disclosed. The amplifier module includes a package, input and output terminals, two or more amplifying units including the first unit and the final unit, an output bias terminal for supplying an output bias to one of amplifying units except for the final unit, and an input bias terminal for supplying an input bias to another one of the amplifying units except for the first unit. A feature of the amplifier module is that the output bias terminal and the input bias terminal are disposed in axial symmetry with respect to a reference axis connecting the input terminal with the output terminal in one side of the package.
    Type: Grant
    Filed: July 28, 2020
    Date of Patent: December 20, 2022
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventor: Naoyuki Miyazawa
  • Patent number: 11533031
    Abstract: Amplifiers, amplification circuits, and phase shifters, for example, for flexibly adjusting an output phase to thereby meet a requirement of a constant phase on a link in a communications field, are provided. In one aspect, an amplifier includes first, second, and third MOS transistors. The first MOS transistor includes a gate separately coupled to a signal input end and a bias voltage input end, a source coupled to a power supply, and a drain separately coupled to sources of the second and third MOS transistors. A drain of the third MOS transistor is coupled to a ground, and a drain of the second MOS transistor is coupled to a signal output end. The bias voltage input end is configured to receive a bias voltage to adjust a phase difference between an input signal at the signal input end and an output signal at the signal output end.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: December 20, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Keji Cui, Yongli Wang, Lei Lu
  • Patent number: 11522506
    Abstract: Various embodiments relate to an integrated circuit including a transistor device having input and output terminals, and an inductor-capacitor (LC) circuit coupled to one of the terminals of the transistor device. The LC circuit includes a capacitor having a top plate and a bottom plate, a inductor having a coil structure, and a connector configured to couple the inductor and an interior portion the top plate of the capacitor. The inductor at least partially overlaps the capacitor.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: December 6, 2022
    Assignee: NXP B.V.
    Inventors: Vikas Shilimkar, Kevin Kim, Joseph Gerard Schultz
  • Patent number: 11515849
    Abstract: A first correction voltage generation circuit provides a first positive or negative correction voltage for correcting an input voltage. A second correction voltage generation circuit provides a second correction voltage identical in polarity to the first correction voltage in accordance with the first correction voltage. The second correction voltage is generated to have a temperature coefficient reverse in polarity to a temperature coefficient of the first correction voltage.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: November 29, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Tomokazu Kojima
  • Patent number: 11509271
    Abstract: A power amplifier module includes an output-stage amplifier, a driver-stage amplifier, an input switch, an output switch, an input matching circuit, an inter-stage matching circuit, an output matching circuit, and a control circuit. The input switch selectively connects one of a plurality of input signal paths to an input terminal of the driver-stage amplifier. The output switch selectively connects one of a plurality of output signal paths to an output terminal of the output-stage amplifier. The control circuit controls operations of the driver-stage amplifier and the output-stage amplifier. The input switch, the output switch, and the control circuit are integrated into an IC chip. The control circuit is disposed between the input switch and the output switch.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 22, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Hiroshi Okabe
  • Patent number: 11502652
    Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Nosun Park
  • Patent number: 11502655
    Abstract: A logarithmic amplifier circuit includes an adaptive gain amplifier circuit and a transistor. The adaptive gain amplifier circuit includes a gain stage and a diode. The gain stage includes an input terminal, and an output terminal. The diode includes a cathode terminal coupled to the output terminal, and an anode terminal coupled to a common terminal. The transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the common terminal, and a third terminal coupled to the output terminal.
    Type: Grant
    Filed: July 24, 2020
    Date of Patent: November 15, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Martijn Fridus Snoeij, Marco Corsi
  • Patent number: 11502656
    Abstract: A variable gain amplifier includes a first transistor group which is connected to an input terminal and an output terminal, and which amplifies a signal from the input terminal to output the amplified signal to the output terminal; a second transistor group connected to the input terminal; a third transistor group connected to the output terminal; and a controller configured to control the first transistor group, the second transistor group, and the third transistor group so that a total number of the number of transistors to be turned on in the first transistor group and the second transistor group is kept at a constant value, and total numbers of transistors to be turned on in the first transistor group and in the third transistor group are the same.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 15, 2022
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Wataru Yamamoto, Koji Tsutsumi, Mitsuhiro Shimozawa
  • Patent number: 11496096
    Abstract: A first module is configured to, based on an input sample, determine a first duty cycle. A second module is configured to, based on a battery voltage and the first duty cycle, determine a second duty cycle. A third module is configured to: set a scalar value based on at least one of a battery current, an amplitude of the input sample, the second duty cycle, and an output voltage; and generate a start signal at a rate equal to a predetermined rate multiplied by the scalar value. A fourth module is configured to set a third duty cycle based on the second duty cycle and the scalar value. A fifth module is configured to generate a PWM output based on the start signal and the third duty cycle. A sixth module is configured to apply power to gates of FETs of a voltage converter based on the PWM output.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: November 8, 2022
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Cary Delano, Doug Heineman, Graeme Docherty, Feng Yu
  • Patent number: 11489500
    Abstract: A differential amplifier of a memory controller may include: an amplification stage configured to amplify input differential signals to generate intermediate differential signals; a control circuit configured to control slew rates for the intermediate differential signals; and an output circuit configured to selectively perform one or more switching operations according to the intermediate differential signals to generate output differential signals.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: November 1, 2022
    Assignee: SK hynix Inc.
    Inventor: Keun Jin Chang
  • Patent number: 11482977
    Abstract: An amplifier circuit structure can include an amplifier located in a main path, and a first switch located in a bypass. One end of a second switch is a signal output end of the amplifier circuit structure, and the other end of the second switch is configured to selectively connect to a signal output end of the bypass or a signal output end of the main path. The first and second switches are configured to control their respective operating states when a first instruction is received, such that the main path is connected to the signal input end and the signal output end of the amplifier circuit structure; and to control their respective operating states when a second instruction is received, such that the bypass is connected to the signal input end of the amplifier circuit structure and the signal output end of the amplifier circuit structure.
    Type: Grant
    Filed: December 12, 2020
    Date of Patent: October 25, 2022
    Assignee: SMARTER MICROELECTRONICS (GUANG ZHOU) CO., LTD.
    Inventors: Yaohua Zheng, Ping Li, Minjun He
  • Patent number: 11482501
    Abstract: Example embodiments relate to amplifiers having improved stability.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: October 25, 2022
    Assignee: Ampleon Netherlands B.V.
    Inventors: Yi Zhu, Josephus Henricus Bartholomeus Van Der Zanden, Rob Mathijs Heeres