Abstract: A semiconductor chip includes a plurality of transistor rows. Corresponding to the plurality of transistor rows, a first bump connected to a collector of the transistor is arranged, and a second bump connected to an emitter is arranged. The transistor rows are arranged along sides of a convex polygon. A first land and a second land provided in a circuit board are connected to the first bump and the second bump, respectively. A first impedance conversion circuit connects the first land and the signal output terminal. A plurality of transistors in the transistor row are grouped into a plurality of groups, and the first impedance conversion circuit includes a reactance element arranged for each of the groups.

Abstract: A sign switching circuitry is disclosed. In one aspect, the sign switching circuitry includes a first and second differential common-source amplifier having common differential input nodes and common differential output nodes configured such that a differential input signal applied at the common differential input nodes is amplified to a differential output signal at the common differential output nodes with a fixed gain by the first amplifier and by the fixed gain with opposite sign by the second amplifier. The sign switching circuitry also includes a switching circuitry configured to activate the first common-source amplifier and deactivate the second common-source amplifier to amplify the differential input signal by the fixed gain, and to activate the second common-source amplifier and deactivate the first common-source amplifier to amplify the differential input signal by the fixed gain with opposite sign.

Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

Abstract: An integrated circuit can include an amplifier coupled to receive an analog input signal, an anti-aliasing filter (AAF) coupled to an output of the amplifier, a buffer circuit coupled to an output of the AAF, a sigma-delta modulator configured to generate a digital data stream in response to an output of the buffer, and a plurality of chopping circuits nested within one another, including a first pair of chopping circuits having at least the amplifier disposed therebetween and configured to remove offset in the analog input signal, and a second pair of chopping circuit having at least the first pair of chopping circuits disposed therebetween. The amplifier, AAF, sigma-delta modulator, and chopping circuits can be formed with the same integrated circuit substrate. Corresponding methods and systems are also disclosed.

Abstract: A biosensor for an analyte monitoring system. In one embodiment, the biosensor includes a cascode common source transimpedance amplifier circuit, an analog to digital converter, and an output circuit. The cascode common source transimpedance amplifier circuit is configured to receive an electrical current generated by an electrochemical reaction of an analyte on a test strip. The cascode common source transimpedance amplifier circuit is also configured to convert the electrical current to an analog voltage signal. The analog to digital converter is configured to convert the analog voltage signal to a digital voltage signal. The output circuit is configured to transmit a signal indicating a measured level of the analyte based on the digital voltage signal.

Abstract: The present invention discloses a bias compensation circuit. The bias compensation circuit includes a detecting circuit, including a diode-connected transistor circuit, with a first end for receiving a first current, and a second end coupled to a first reference voltage end; and a first diode circuit, with a first end for receiving a second current, and a second end coupled to the first reference voltage end; wherein the detecting circuit provides a first voltage level according to the diode-connected transistor circuit, and provides a second voltage level according to the first diode circuit; a voltage-current converting circuit, coupled to the detecting circuit, for generating a first reference current according to the first voltage level and the second voltage level; and a bias circuit, coupled to the voltage-current converting circuit, for receiving the first reference current, to provide a bias voltage level according to the first reference current.

Abstract: An amplifying circuit including a first gain circuit, a second gain circuit, a Miller capacitor, a positive feedback circuit and a feedforward gain circuit. The second gain circuit is configured to receive a first gain signal from the first gain circuit and generate a second gain signal. The Miller capacitor, the positive feedback circuit and the feedforward gain circuit are electrically coupled between an input terminal and an output terminal of the second gain circuit. The positive feedback circuit is configured to feedback the signal of the output terminal of the second gain circuit to the input terminal of the second gain circuit. The feedforward gain circuit is configured to amplify the first gain signal to output a third gain signal to the output terminal of the second gain circuit.

Abstract: In a discrete supply modulation system, a circuit includes a multi-stage pulse shaping network (PSN) having a first PSN stage having an input configured to receive variable bias supply signals from a power management circuit (PMC) and having an output coupled to one or more second PSN stages with each of the one or more second PSN stages having an output configured to be coupled to a supply (or bias) terminal of a respective one of one or more radio frequency amplifiers. Such an arrangement is suitable for use with transmit systems in mobile handsets operating in accordance with 5th generation (5G) communications and other connectivity protocols such as 802.11 a/b/g/n/ac/ax/ad/ay and is suitable for use with multiple simultaneous transmit systems including multiple-input, multiple-output (MIMO), uplink carrier aggregation (ULCA) and beamforming.

Abstract: A variable gain amplifier system includes a variable gain amplifier circuit configured to receive an input signal, apply a gain to the input signal, and generate an output signal in accordance with the gain applied to the input signal. The variable gain amplifier circuit is further configured to receive a gain control signal and a bandwidth control signal. A control module is configured to generate the gain control signal to adjust the gain of the variable gain amplifier circuit and generate, separately from the gain control signal, the bandwidth control signal to adjust a bandwidth of the variable gain amplifier circuit by selectively varying an amount of inductance contributed by an inductor circuit of the variable gain amplifier circuit.

Abstract: A circuit includes a first transconductance stage having an output. The circuit further includes an output transconductance stage, and a first source-degenerated transistor having a first control input and first and second current terminals. The first control input is coupled to the output of the first transconductance stage. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal is coupled to the second current terminal and to the output transconductance stage.

Abstract: An amplifier has a first amplifying circuit configured to receive a voltage input and to output an amplified current, a second amplifying circuit configured to receive the amplified current and to output an amplified voltage, the second amplifying circuit comprising a pair of feedback resistive elements, each feedback resistive element being coupled to a gate and drain of a corresponding transistor in a pair of output transistors in the second amplifying circuit, and a feedback circuit configured to provide a negative feedback loop between an input and an output of the pair of output transistors, the feedback circuit including a first transconductance amplification circuit and a first equalizing circuit.

Abstract: According to one embodiment, a clipping state detecting circuit includes: a zero-cross detection circuit that detects a zero-cross point of an input signal; an output circuit that converts the input signal into a PWM signal; a clip detection circuit that detects a state in which an output of the output circuit is clipped; and a control circuit that determines a state is a clipping state when a clip time of the output of the output circuit satisfies a condition of a threshold value set in advance with respect to a non-clip time.

Abstract: A power converter may include an input for receiving an input signal and output for generating an intermediate signal that is a power converted signal from the input signal wherein the intermediate signal is determined based on various parameters of a signal path that utilizes the intermediate signal, wherein the various parameters comprise one or more of the following: a peak output signal of the signal path, energy requested over a period of time by the signal path, available energy from an energy source to the power converter, stored energy at an output of the power converter, and stored energy of a battery for providing electrical energy at the input.

Abstract: Apparatus and methods for bias switching of power amplifiers are provided herein. In certain configurations, a power amplifier system includes a power amplifier that provides amplification to a radio frequency (RF) signal and a bias control circuit that biases the power amplifier. The power amplifier includes an amplification transistor that receives the RF signal at an input, and a first bias network and a second bias network each connected to the input. The bias control circuit includes a first switch, a first reference current source that provides the first reference current to the first bias network through the first switch, a second switch, and a second reference current source that provides the second reference current to the second bias network through the second switch.

Abstract: Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

Abstract: Embodiments are described herein for power generation systems and methods that use quadrature splitters and combiners to facilitate plasma stability and control. For one embodiment, a quadrature splitter receives an input signal and generates a first and second signals as outputs with the second signal being ninety degrees out of phase with respect to the first signal. Two amplifiers then generate a first and second amplified signals. A quadrature combiner receives the first and second amplified signals and generates a combined amplified signal that represents re-aligned versions of the first and second amplified signals. The power amplifiers can be combined into a system to generate a high power output to a processing chamber. Further, detectors can generate measurements used to monitor and control power generation. The power amplifiers, system, and methods provide significant advantages for high-power generation delivered to process chambers for plasma generation during plasma processing.

Abstract: Apparatus and methods for a modified Doherty amplifier operating at gigahertz frequencies are described. The combining of signals from a main amplifier and a peaking amplifier occur prior to impedance matching of the amplifier's output to a load. An output impedance-matching element can be relied upon. In one example, the output impedance-matching element can include an output strip line, a shunt capacitor connected between the output strip line and ground, an output capacitor connected between the output strip line and an output bonding pad, and an inductive strip line connected between the output bonding pad and ground.

Abstract: Devices, systems, and methods for multi-channel common-mode coupled alternating current (AC) gain amplifiers (MC-CM-AC Amp) are disclosed. The MC-CM-AC Amp can comprise a first operational amplifier including: a first non-inverting input port configured to be coupled to a first input signal, and a first inverting input port configured to be coupled to a first capacitor. The MC-CM-AC Amp can comprise a second operational amplifier including a second non-inverting input port configured to be coupled to a second input signal, and a second inverting input port configured to be coupled to a second capacitor. The MC-CM-AC Amp can comprise one or more gain-setting resistors configured to be coupled between the first capacitor and the second capacitor.

Abstract: Disclosed is envelope tracking circuitry having an envelope tracking integrated circuit (ETIC) coupled to a power supply to provide an envelope tracked power signal to a power amplifier (PA) with a filter equalizer configured to inject an error-correcting signal into the ETIC in response to equalizer settings. Further included is PA resistance estimator circuitry having a first peak detector circuit configured to capture within a window first peaks associated with a sense current generated by the ETIC, a second peak detector circuit configured to capture within the window second peaks associated with a scaled supply voltage corresponding to the envelope tracked power signal, comparator circuitry configured to receive the first peaks and receive the second peaks and generate an estimation of PA resistance, and an equalizer settings correction circuit configured to receive the estimation of PA resistance and update the equalizer settings in response to the estimation of PA resistance.