Patents Examined by Khiem D Nguyen
  • Patent number: 11121069
    Abstract: A semiconductor package includes a semiconductor chip including a connection pad disposed on an active surface of the semiconductor chip, a passivation layer disposed on the connection pad and the active surface and having an opening exposing at least a portion of the connection pad, and a capping pad covering the connection pad exposed to the opening; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the active surface of the semiconductor chip and including a connection via connected to the capping pad and a redistribution layer connected to the connection via, wherein the capping pad includes: a central portion disposed in the opening, and a peripheral portion extending from the central portion onto the passivation layer, and having a crystal grain having a size different from that of the crystal grain of the central portion.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: September 14, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jaehoon Choi, Doohwan Lee, Byungho Kim, Jooyoung Choi
  • Patent number: 11121679
    Abstract: An amplifying apparatus is provided. The amplifying apparatus comprises an amplifying circuit comprising a power amplifier and a bias circuit, the bias circuit is configured to detect an ambient temperature of the power amplifier to output a temperature voltage and regulate an internal current based on an input control signal to supply a bias current obtained by the regulation to the power amplifier; and a temperature control circuit that generates the control signal based on the temperature voltage during initial driving from a transmission mode starting point in time to an input point in time at which an input signal is input and outputting the control signal to the amplifying circuit.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: September 14, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Wong Jang, Byeong Hak Jo, Jeong Hoon Kim, Jong Ok Ha, Hyun Paek, Shinichi Iizuka
  • Patent number: 11121297
    Abstract: A method of manufacturing a light emitting device includes: mounting a light emitting element in a package in which a recess is defined, the light emitting element being mounted on a bottom surface defining the recess; forming a first reflecting layer by covering lateral surfaces defining the recess with a first resin containing a first reflecting material; forming a second reflecting layer covering the bottom surface defining the recess, wherein the step of forming the second reflecting layer comprises settling the second reflecting material in the second resin by a centrifugal force so as to form (i) a layer containing a second reflecting material on the bottom surface defining the recess, and (ii) a light-transmissive layer above the layer containing the second reflecting material; and disposing a phosphor-containing layer on the second reflecting layer and the light emitting element, the phosphor-containing layer comprising a third resin that contains a phosphor.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: September 14, 2021
    Assignee: NICHIA CORPORATION
    Inventors: Kenji Ozeki, Atsushi Kojima, Chinami Nakai
  • Patent number: 11114437
    Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: September 7, 2021
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 11114538
    Abstract: A microelectronic transistor may be fabricated having an airgap spacer formed as a gate sidewall spacer, such that the airgap spacer is positioned between a gate electrode and a source contact and/or a drain contact of the microelectronic transistor. As the dielectric constant of gaseous substances is significantly lower than that of a solid or a semi-solid dielectric material, the airgap spacer may result in minimal capacitive coupling between the gate electrode and the source contact and/or the drain contact, which may reduce circuit delay of the microelectronic transistor.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 7, 2021
    Assignee: Intel Corporation
    Inventors: Chen-Guan Lee, Joodong Park, En-Shao Liu, Everett S. Cassidy-Comfort, Walid M. Hafez, Chia-Hong Jan
  • Patent number: 11114396
    Abstract: In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: September 7, 2021
    Assignee: Cree, Inc.
    Inventors: Lei Zhao, Mario Bokatius
  • Patent number: 11114597
    Abstract: A display device is provided. The display device includes a substrate and a first metal line and a second metal line disposed on the substrate. The display device includes a first pad and a second pad disposed on the substrate and electrically connected to the first metal line and the second metal line respectively. The display device further includes an electronic device disposed on the first pad and the second pad. The electronic device includes a first connecting post and a second connecting post, wherein a distance between the first connecting post and the second connecting post is in a range from 1 um to 200 um. A portion of the first connecting post is embedded in the first pad and a portion of the second connecting post is embedded in the second pad.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: September 7, 2021
    Assignee: INNOLUX CORPORATION
    Inventors: Jia-Yuan Chen, Tsung-Han Tsai, Kuan-Feng Lee, Yuan-Lin Wu
  • Patent number: 11114984
    Abstract: An audio device for reducing pop noise is adapted to compensate for a direct current (DC) offset of an audio source signal and output the audio source signal to an audio playing device. The audio device includes a linear operation circuit, an adder, a digital-to-analog circuit, and an amplification circuit. The digital-to-analog circuit is coupled between the adder and the amplification circuit. The linear operation circuit generates a DC offset value based on a linear equation, a temperature parameter, a slope parameter, and a constant. The adder is configured to process an input signal and the DC offset value to generate a calibration signal. The digital-to-analog circuit is configured to convert a calibration signal in a digital form to a calibration signal in an analog form. The amplification circuit is configured to process the calibration signal in the analog form to output the audio source signal.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 7, 2021
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Shih-Hsin Lin, Che-Hung Lin, Yi-Chang Tu
  • Patent number: 11107767
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first plurality of interconnect layers within a first inter-level dielectric (ILD) structure disposed along a front-side of a first substrate. A conductive pad is arranged along a back-side of the first substrate and a first through-substrate-via (TSV) extends between an interconnect wire of the first plurality of interconnect layers and the conductive pad. A second plurality of interconnect layers are within a second ILD structure disposed along a front-side of a second substrate that is bonded to the first substrate. A second through substrate via (TSV) extends through the second substrate. The second TSV has a greater width than the first TSV.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: August 31, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Hsun-Ying Huang
  • Patent number: 11108363
    Abstract: An envelope tracking (ET) circuit and related power amplifier apparatus is provided. An ET power amplifier apparatus includes an ET circuit and a number of amplifier circuits. The ET circuit is configured to provide a number of ET modulated voltages to the amplifier circuits for amplifying concurrently a number of radio frequency (RF) signals. The ET circuit includes a target voltage circuit for generating a number of ET target voltages adapted to respective power levels of the RF signals and/or respective impedances seen by the amplifier circuits, a supply voltage circuit for generating a number of constant voltages, and an ET voltage circuit for generating the ET modulated voltages based on the ET target voltages and a selected one of the constant voltages. By employing a single ET circuit, it may be possible to reduce the footprint and improve heat dissipation of the ET power amplifier apparatus.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: August 31, 2021
    Assignee: Qorvo US, Inc.
    Inventor: Nadim Khlat
  • Patent number: 11094806
    Abstract: A method to fabricate a transistor, the method comprising: implanting dopants in a semiconductor to form a collector region having majority carriers of a first type; implanting dopants with a first dosage and implanting dopants with a second dosage in the collector region to form a base region having majority carriers of a second type, wherein the second dosage is at a lower energy than the first dosage; forming a gate oxide on the base region; forming a gate material on the gate oxide; forming the gate material and the gate oxide to leave uncovered an emitter area of the base region; and implanting dopants in the emitter area to form an emitter region having majority carriers of the first type.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 17, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Alexei Sadovnikov, Natalia Lavrovskaya
  • Patent number: 11094617
    Abstract: A semiconductor package comprises a lead frame, a first field-effect transistor (FET), a second low side FET, a first high side FET, a second high side FET, a first metal clip, a second metal clip, and a molding encapsulation. The semiconductor package further comprises an optional integrated circuit (IC) controller or an optional inductor. A method for fabricating a semiconductor package. The method comprises the steps of providing a lead frame; attaching a first low side FET, a second low side FET, a first high side FET, and a second high side FET to the lead frame; mounting a first metal clip and a second metal clip; forming a molding encapsulation; and applying a singulation process.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: August 17, 2021
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN), LTD.
    Inventor: Yan Xun Xue
  • Patent number: 11094678
    Abstract: A light emitting device includes: a substrate; a first electrode and a second electrode on the substrate and spaced apart from each other; a light emitting diode between the first electrode and the second electrode and connected to the first and second electrodes; a first contact on the first electrode; and a second contact on the second electrode. The first contact contacts the first electrode and a first portion of the light emitting diode, and the second contact contacts the second electrode and a second portion of the light emitting diode.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 17, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeoung Keol Woo, Chul Min Bae, Heon Sik Ha
  • Patent number: 11095256
    Abstract: A semiconductor device includes three transistors, five switches, two inductors, and a capacitor. A first transistor has a gate. The switches have one terminal connected in series with a drain of the first transistor in parallel. A second transistor has a source connected to the first switch and a grounded gate. A third transistor having a source connected to the second switch and a grounded gate. A first inductor and a second inductor each has one terminal connected in series with the third switch in parallel. A fourth switch has one terminal connected to the first inductor and another terminal connected to the source of the second transistor. A fifth switch has one terminal connected to the second inductor and another terminal connected to the source of the third transistor. A capacitor connected between the one terminal of the fourth switch and the one terminal of the fifth switch.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: August 17, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Toshiki Seshita, Yasuhiko Kuriyama
  • Patent number: 11094690
    Abstract: A semiconductor device having a P type substrate, an N type layer on the P type substrate that forms a PN junction therewith and the P type region, N type region and P type substrate form at least one parasitic PNP transistor.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: August 17, 2021
    Assignee: Board Of Trustees Of The University Of Arkansas
    Inventors: Zhong Chen, Farzan Farbiz
  • Patent number: 11088017
    Abstract: A method of forming a semiconductor structure includes forming a sacrificial material over a stack comprising alternating levels of a dielectric material and another material, forming an opening through the sacrificial material and at least some of the alternating levels of the dielectric material and the another material, forming at least one oxide material in the opening and overlying surfaces of the sacrificial material, an uppermost surface of the at least one oxide material extending more distal from a surface of a substrate than an uppermost level of the dielectric material and the another material, planarizing at least a portion of the at least one oxide material to expose a portion of the sacrificial material, and removing the sacrificial material while the uppermost surface of the at least one oxide material remains more distal from the surface of the substrate than the uppermost level of the alternating levels of the dielectric material and the another material.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Micron Technology, Inc.
    Inventors: John B. Matovu, David S. Meyaard, Gowrisankar Damarla, Sri Sai Sivakumar Vegunta, Kunal Shrotri, Shashank Saraf, Kevin R. Gast, Jivaan Kishore Jhothiraman, Suresh Ramarajan, Lifang Xu, Rithu K. Bhonsle, Rutuparna Narulkar, Matthew J. King
  • Patent number: 11087990
    Abstract: A semiconductor device includes a stacked structure on a substrate. The stacked structure includes stepped regions and a central region between the stepped regions, an upper insulation layer on the stacked structure, and a capping insulation layer on the stepped regions of the stacked structure. The capping insulation layer includes a first upper end portion and a second upper end portion that are adjacent to the upper insulation layer. The upper insulation layer is between the first upper end portion and the second upper end portion. The first upper end portion and the second upper end portion extends a first height relative to the substrate that is different from a second height relative to the substrate of the second upper end portion.
    Type: Grant
    Filed: June 6, 2019
    Date of Patent: August 10, 2021
    Inventors: Chang Sun Hwang, Han Sol Seok, Hyun Ku Kang, Byoung Ho Kwon, Chung Ki Min
  • Patent number: 11070180
    Abstract: A class AB buffer includes an output stage and an input stage. The output stage includes a first output transistor and a second output transistor. The second output transistor is coupled to the first output transistor. The input stage is coupled to the output stage. The input stage includes a first cascode transistor, a first switch, a second cascode transistor, and a second switch. The first switch is coupled to the first cascode transistor and the first output transistor. The second switch is coupled to the first switch, the second cascode transistor, and the first output transistor.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: July 20, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Nitin Agarwal, Aniruddha Roy
  • Patent number: 11069569
    Abstract: A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, on the substrate and including a plurality of open portions. The plurality of open portions have shapes extending longer in the second direction than in the first direction, and when viewed from inner sides of the plurality of open portions, the plurality of open portions are convex in the first direction and are concave in the second direction.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: July 20, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-hoon Kim
  • Patent number: 11056495
    Abstract: A structure of memory device includes trench isolation lines in a substrate, extending along a first direction. An active region in the substrate is between adjacent two of the trench isolation lines. A dielectric layer is disposed on the active region of the substrate. A floating gate corresponding to a memory cell is disposed on the dielectric layer between adjacent two of the trench isolation lines. The floating gate has a first protruding structure at a sidewall extending along the first direction. A first insulating layer crosses over the floating gate and the trench isolation lines. A control gate line is disposed on the first insulating layer over the floating gate, extending along a second direction intersecting with the first direction. The control gate line has a second protruding structure correspondingly stacked over the first protruding structure of the floating gate.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: July 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Liang Yi, Zhiguo Li, Chi Ren, Qiuji Zhao, Boon Keat Toh