Patents Examined by Khiem D Nguyen
  • Patent number: 10707328
    Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li
  • Patent number: 10707331
    Abstract: A method includes forming a fin structure on a substrate, forming a dummy gate structure wrapped around the fin structure, depositing an Interlayer Dielectric (ILD) layer over the fin structure, removing the dummy gate structure to expose a portion of the fin structure, and performing an etching process on the portion of the fin structure to reduce a width of the portion of the fin structure.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: July 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ka-Hing Fung, Chen-Yu Hsieh, Che-Yuan Hsu, Ming-Yuan Wu, Hsu-Chieh Cheng
  • Patent number: 10707342
    Abstract: Disclosed is a transistor device and a method for producing thereof. The transistor device includes at least one transistor cell, wherein the at least one transistor cell includes: a source region, a body region and a drift region in a semiconductor body; a gate electrode dielectrically insulated from the body region by a gate dielectric; a field electrode dielectrically insulated from the drift region by a field electrode dielectric; and a contact plug extending from a first surface of the semiconductor body to the field electrode and adjoining the source region and the body region.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: July 7, 2020
    Assignee: Infineon Technology Austria AG
    Inventors: Markus Zundel, Franz Hirler
  • Patent number: 10700655
    Abstract: An integrated circuit is disclosed for gain-dependent impedance matching and linearity. The integrated circuit includes at least two amplifier branches, an input inductor, and at least two degeneration inductors. Each amplifier branch includes a node, an input transistor, and a cascode stage connected between a drain of the input transistor and the node. Respective nodes of the at least two amplifier branches are connected together and respective gates of the input transistors of the at least two amplifier branches are connected together. The input inductor is connected to the respective gates, and the at least two degeneration inductors are connected between respective sources of the input transistors of the at least two amplifier branches and a ground. The at least two degeneration inductors are configured to establish a magnetic coupling with the input inductor and establish another magnetic coupling between each other.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 30, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Alaaeldien Mohamed Abdelrazek Medra, David Zixiang Yang, Kevin Hsi Huai Wang, Chen Zhai, Francesco Gatta
  • Patent number: 10700653
    Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 30, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Konstantinos Manetakis, Thomas G. McKay
  • Patent number: 10700646
    Abstract: pHEMT-based switch circuits, devices including same, and methods of improving the linearity thereof. In one example, an antenna switch module includes a pHEMT switching circuit connected in series between an input signal terminal and a load terminal, the pHEMT switching circuit including at least one pHEMT configured to produce a first harmonic signal at the load terminal responsive to being driven by an input signal of a fundamental frequency received at the input signal terminal, the first harmonic signal having a first phase, and a gate resistance circuit connected to a gate of the at least one pHEMT and having a resistance value selected to produce a second harmonic signal at the load terminal, the second harmonic signal having a second phase opposite to the first phase.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: June 30, 2020
    Assignee: SKYWORKS SOLUTIONS, INC.
    Inventors: Fikret Altunkilic, Haki Cebi, Yu Zhu, Cejun Wei, Jerod F. Mason
  • Patent number: 10692849
    Abstract: Disclosed herein is a semiconductor integrated circuit device which includes a standard cell with a plurality of fins extending in a first direction and arranged in a second direction that is perpendicular to the first direction. An active fin of the fins forms part of an active transistor. A dummy fin of the fins is disposed between the active fin and an end of the standard cell.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: June 23, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10685877
    Abstract: A semiconductor device includes: a plurality of lower electrodes arranged on a substrate in a first direction, which is parallel to a main surface of the substrate, and a second direction parallel to the main surface of the substrate and perpendicular to the first direction; and a support structure pattern configured to connect the plurality of lower electrodes to each other to support the plurality of lower electrodes, on the substrate and including a plurality of open portions. The plurality of open portions have shapes extending longer in the second direction than in the first direction, and when viewed from inner sides of the plurality of open portions, the plurality of open portions are convex in the first direction and are concave in the second direction.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 16, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ji-hoon Kim
  • Patent number: 10686415
    Abstract: Various examples are directed to a power amplifier circuit, comprising a digital predistortion circuit, first and second power amplifiers, and a bias feedback circuit. The digital predistortion circuit may be configured to generate a predistorted input signal based at least in part on an input signal. The first power amplifier may be configured to generate a first amplified signal based at least in part on the predistorted input signal. The second power amplifier may be configured to generate a second amplified signal based at least in part on the predistorted input signal. The bias feedback circuit may be configured to adjust at least one of a bias of the first power amplifier or a bias of the second power amplifier to align a first nonlinear behavior of the first power amplifier with a second nonlinear behavior of the second power amplifier.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: June 16, 2020
    Inventors: Patrick Pratt, Rafael Celedon
  • Patent number: 10686409
    Abstract: An amplifier circuit configuration capable of processing non-contiguous intra-band carrier aggregate (CA) signals using amplifiers is disclosed herein. In some cases, each of a plurality of amplifiers is an amplifier configured as a cascode (i.e., a two-stage amplifier having two transistors, the first configured as a “common source” input transistor, e.g., input field effect transistor (FET), and the second configured in a “common gate” configuration as a cascode output transistor, (e.g. cascode output FET). In other embodiments, the amplifier may have additional transistors (i.e., more than two stages and/or stacked transistors). The amplifier circuit configuration can be operated in either single mode or split mode. A switchable coupling is placed between the drain of the input FETs of each amplifier within the amplifier circuit configuration.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 16, 2020
    Assignee: pSemi Corporation
    Inventors: Kashish Pal, Emre Ayranci, Miles Sanner
  • Patent number: 10672701
    Abstract: Discussed generally herein are methods and devices for flexible fabrics or that otherwise include thin traces. A device can include a flexible polyimide material, and a first plurality of traces on the flexible polyimide material, wherein the first plurality of traces are patterned on the flexible polyimide material using laser spallation.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: June 2, 2020
    Assignee: Intel Corporation
    Inventors: Vivek Raghunathan, Yonggang Li, Aleksandar Aleksov, Adel A. Elsherbini, Johanna M. Swan
  • Patent number: 10672740
    Abstract: Methods and systems for a semiconductor package with high routing density routing patch are disclosed and may include a semiconductor die bonded to a substrate and a high routing density patch bonded to the substrate and to the semiconductor die, wherein the high routing density patch comprises a denser trace line density than the substrate. The high routing density patch can be a silicon-less-integrated module (SLIM) patch, comprising a BEOL portion, and can be TSV-less. Metal contacts may be formed on a second surface of the substrate. A second semiconductor die may be bonded to the substrate and to the high routing density patch. The high routing density patch may provide electrical interconnection between the semiconductor die. The substrate may be bonded to a silicon interposer. The high routing density patch may have a thickness of 10 microns or less. The substrate may have a thickness of 10 microns or less.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 2, 2020
    Assignee: Amkor Technology, Inc.
    Inventors: Michael Kelly, Ronald Patrick Huemoeller, David Jon Hiner
  • Patent number: 10665627
    Abstract: A method for forming an image sensor device is provided. The method includes forming an isolation structure in a substrate. The method includes forming a light-sensing region in the substrate. The isolation structure surrounds the light-sensing region. The method includes forming a grid layer over the substrate. The grid layer is over the isolation structure and has an opening over the light-sensing region. The method includes forming a first lens in or over the opening. The method includes forming a second lens over the first lens and the grid layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Shih-Hsun Hsu
  • Patent number: 10665593
    Abstract: Some embodiments include a memory cell having a transistor with a channel region between a first source/drain region and a second source/drain region. A controlled-conductivity region is adjacent the first source/drain region. The controlled-conductivity region has a low-conductivity mode and a high-conductivity mode. The high-conductivity mode has a conductivity at least 106 greater than a conductivity of the low-conductivity mode. The channel region includes a first material having a first bandgap, and the controlled-conductivity region includes a second material having a second bandgap which is greater than the first bandgap. A charge-storage device is electrically coupled to the first source/drain region through the controlled-conductivity region. A bitline is electrically coupled to the second source/drain region.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: May 26, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej S. Sandhu, Kamal M. Karda
  • Patent number: 10651806
    Abstract: Methods and systems for a pseudo-differential low-noise amplifier at Ku-band may comprise a low-noise amplifier (LNA) integrated on a semiconductor die, where the LNA includes first and second differential pair transistors with an embedded inductor tail integrated on the semiconductor die. The embedded inductor tail may include: a first inductor with a first terminal capacitively-coupled to a gate terminal of the first differential pair transistor and a second terminal of the first inductor coupled to second, third, and fourth inductors. The second inductor may be coupled to a source terminal of the first differential pair transistor, the fourth inductor may be coupled to a source terminal of the second differential pair transistor, and the third inductor may be capacitively-coupled to a gate terminal of the second differential pair transistor and also to ground. The second inductor may be embedded within the first inductor.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 12, 2020
    Assignee: MAXLINEAR, INC.
    Inventors: Abhishek Jajoo, Vamsi Paidi
  • Patent number: 10651812
    Abstract: Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 12, 2020
    Assignee: Skyworks Solutions, Inc.
    Inventors: Ambarish Roy, Eric Marsan, Stephen Richard Moreschi
  • Patent number: 10651801
    Abstract: Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: May 12, 2020
    Assignee: Cirrus Logic, Inc.
    Inventors: Lei Zhu, Xin Zhao, John L. Melanson
  • Patent number: 10651175
    Abstract: Disclosed herein is a semiconductor device including two standard cells which are arranged adjacent to each other in an X direction. One of the two standard cells includes a plurality of first fins which extend in the X direction, and which are arranged along a boundary between the two standard cells in a Y direction. The other standard cell includes a plurality of second fins which extend in the X direction, and which are arranged along the boundary between the two standard cells in the Y direction. The plurality of second fins includes a dummy fin.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: May 12, 2020
    Assignee: SOCIONEXT INC.
    Inventor: Hiroyuki Shimbo
  • Patent number: 10644003
    Abstract: A semiconductor memory device includes a substrate having an active region, word lines extending across the active region, a bit line on the active region between the word lines, a bit line node contact between the bit line and the active region, and a storage node contact on an end portion of the active region, wherein one or more of the bit line node contact or the storage node contact include silicon germanium.
    Type: Grant
    Filed: July 27, 2017
    Date of Patent: May 5, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Min Hee Cho, Satoru Yamada, Junsoo Kim, Honglae Park, Wonsok Lee, Namho Jeon
  • Patent number: 10636808
    Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Byoung Taek Kim, Jun Hee Lim