Abstract: An apparatus comprises a processing device that includes a processor coupled to a memory. The processing device is configured to identify a source multi-path device in first multi-pathing software, to create a target multi-path device in second multi-pathing software different than the first multi-pathing software, to copy a set of paths of the source multi-path device to the target multi-path device, to add to the set of paths of the source multi-path device a new path to the target multi-path device, and to remove paths other than the new path from the source multi-path device. Such an arrangement illustratively provides non-disruptive switching of path selection functionality of a host device from the source multi-path device of the first multi-pathing software to the target multi-path device of the second multi-pathing software. The source and target multi-path devices illustratively utilize different storage access protocols, such as respective SCSI and NVMe access protocols.

Abstract: An object-based data storage service receives a request to store a data object in association with a smart data storage tier. Based at least in part on characteristics of the data object, the object-based data storage service identifies and stores the data object in a first location corresponding to a first data storage tier. The object-based data storage service monitors access to the data object to identify a second set of characteristics of the data object. This second set of characteristics is used to determine that the data object is to be transitioned to a second data storage tier. The object-based data storage service, based at least in part on this determination, stores the data object in a second location corresponding to the second data storage tier.

Abstract: Disclosed are a solid state drive and a write operation method. The solid state drive comprises: a controller, receiving write data from outside and comprising a first cache unit for storing the write data; a Flash memory, receiving the write data sent by the first cache unit according to a first instruction of the controller; a second cache unit, storing the write data from the first cache unit as backup data, and sending the backup data to the Flash memory according to a second instruction of the controller. The second instruction is obtained after the write data fails to be written into the Flash memory under the first instruction, so that the backup data can continue to be called if write operation fails. By combining advantages of the first and second cache units, efficiency and quality of write operations are improved and bandwidth requirements are lowered.

Abstract: A Near Memory Processing (NMP) module including: a plurality of memory units; an Input/Output (I/O) interface configured to receive commands from a host system, wherein the host system includes a host memory controller configured to access the plurality of memory units; a decoder configured to decode the commands and generate a trigger; and an NMP memory controller configured to: receive the trigger from the decoder; and generate a signal in response to the trigger to synchronize the NMP module with the host system.

Abstract: Methods, systems, and devices for idle mode temperature control for memory systems are described. A memory system may implement the use of one or more dummy access commands to reduce the effects of errors introduced by temperature changes while the memory system is in an idle mode. For example, performing one or more access commands, such as one or more read commands, may increase a temperature of a memory device and support a desired operating temperature for the memory device while the memory system is in the idle mode. The memory system may measure the temperature of the memory device during the idle mode. If the memory system determines that the temperature of the memory device has fallen below a threshold temperature, the memory system may issue a quantity of dummy access commands to the memory device, and the corresponding dummy access operations may result in a temperature increase at the memory device.

Abstract: Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.

Abstract: A method and a device are provided. The device includes a first memory, a second memory having a storage characteristic different from that of the first memory, and a processor operatively connected to at least one of the first memory and the second memory. The processor is configured to generate a logical storage area in a data area of the first memory, store designated data in the generated logical storage area, and enter a recovery mode to store the data stored in the logical storage area in the second memory, format the first memory, and move the data stored in the second memory to the data area of the first memory.

Abstract: Embodiments are directed to tiered data store with persistent layers. A write tier in the file system for storing in a file system. A value for a performance metric that corresponds to write requests to the file system may be predicted based on characteristics of the write requests such that the performance metric may be determined based on a plurality of interactions with the write tier. The predicted value that exceeds a threshold value of the performance metric may be employed to cause performance of further actions, including: queuing a portion of the write requests in a memory buffer based on the predicted value and the threshold value; combining the queued portion of the write requests into s; storing the data segments in the write tier such that a measured value of the performance metric may be less than the threshold value.

Abstract: A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.

Abstract: A system and method include creating, by an Availability Group (“AG”) controller in a virtual computing system, a first AG clone from a source database. The source database is stored on a primary replica node of an AG of the virtual computing system. The system and method also include creating, by the Controller, a second AG clone from the first AG clone and storing, by the Controller, the second AG clone on a secondary replica node of the AG. The second AG clone has a size of substantially zero.

Abstract: Methods, systems, and devices for rating-based mapping of data to memory are described. A memory system may determine a first rating for a set of data selected for writing to a memory system. The memory system may select a target page of a block in the memory system for writing the set of data based at least in part on a second rating for the target page. The memory system may write the set of data to the target page based at least in part on the first rating for the set of data corresponding to the second rating for the target page.

Abstract: A system includes a host device, a memory device, and a command manager configured to reorder respective command responses for corresponding commands between the host device and the memory device. The command manager is further configured to receive a command response associated with a transaction identifier for each command. An index value for the command is written to a reordering queue. In response to a command response write for the command response, the index value from the reordering queue is read. The index value is written in an index update queue. A network write index update message is transmitted.

Abstract: A storage device may include a memory device including a plurality of memory dies; and a memory controller configured to control the memory device in units of super blocks each including two or more memory blocks included in the memory device, wherein at least one of the super blocks within the memory device is a super block including a plurality of small multi-die zones each including a portion of each of the memory blocks included in different memory dies among the memory dies, wherein the memory controller is further configured to receive a garbage collection request and information on valid pages included in the small multi-die zone, and to select, among the super blocks within the memory device, a victim super block in response to the garbage collection request and information on valid pages included in the small multi-die zone.

Abstract: Techniques and mechanisms for a victim cache to operate in conjunction with a skewed cache to help mitigate the risk of a side-channel attack. In an embodiment, a first line is evicted from a skewed cache, and moved to a victim cache, based on a message indicating that a second line is to be stored to the skewed cache. Subsequently, a request to access the first line results in a search of both the victim cache and sets of the skewed cache which have been mapped to an address corresponding to the first line. Based on the search, the first line is evicted from the victim cache, and reinserted in the skewed cache. In another embodiment, reinsertion of the first line in the skewed cache includes the first line and a third line being swapped between the skewed cache and the victim cache.

Abstract: A memory controller includes a data detection circuit configured to detect, when power is supplied after a sudden power-off (SPO), a lost write sequence index “M” among the plural write sequence indexes, and detect first data corresponding to a write sequence index “M?1” and second data corresponding to a write sequence index “M+1”; a barrier decision circuit configured to determine, based on whether first barrier information of the first data and second barrier information of the second data are identical with each other, whether a barrier request for the first data has been received from a host; and a data recovery operation determination circuit configured to determine whether to perform a recovery operation on target data corresponding to the write sequence index “M+1” and thereafter based on whether the barrier request for the first data has been received.

Abstract: A method for managing a shared memory, including: setting a master core, applying, by the master core, to a system for idle hugepage blocks, mapping the idle hugepage blocks to a virtual address space of the master core, and sorting the hugepage blocks in an ascending order of physical address size of the hugepage blocks; dividing, depending on whether the physical addresses are continuous, the hugepage blocks sorted into segments; in response to determining that there are segments satisfying the memory demand of the subsystem, sorting the segments satisfying the memory demand of the subsystem in a descending order of lengths thereof, and remapping the sorted segments to obtain segments having both continuous virtual addresses and continuous real addresses; and in response to determine that there is a segment satisfying the memory demand of the system, releasing hugepage blocks other than the segment satisfying the memory demand of the system.

Abstract: A system and method for repartitioning data in a distributed network. The method may include executing, by one or more processors, a first pass of a data set from a plurality of first sources to a plurality of first sinks, each first sink collecting data from one or more of the first sources, and executing, by the one or more processors, a second pass of the data set from a plurality of second sources to a plurality of second sinks, each one of the plurality of first sinks corresponding to one of the plurality of second sources, and each second sink collecting data from one or more of the second sources. Executing the first and second passes causes the data set to be repartitioned such that one or more second sinks collect data that originated from two or more of the first sources.

Abstract: A cartridge management system that manages a plurality of cartridges, in each of which a magnetic tape is housed, includes a processor, and a memory incorporated in or connected to the processor, in which the processor is configured to execute data rewrite-in processing of rewriting data stored in the magnetic tape, in a specific cartridge among the plurality of cartridges based on an access frequency indicating a frequency of access to the data, and cartridge replacement processing of replacing the data stored in the magnetic tape of the specific cartridge and the data stored in the magnetic tape of another cartridge among the plurality of cartridges.

Abstract: A memory device for improving the speed of a program operation and an operating method thereof is provided. The memory device includes a memory cell array including a plurality of memory cells, a voltage generator configured to generate voltages for one or more program operations and a verify operation performed on the plurality of memory cells, a control logic configured to perform a control operation on the plurality of memory cells so that a first program and a second program loop are performed, a second program operation being performed based on a compensation voltage level determined based on a result of the first verify operation, and a plurality of bit lines connected to the memory cell array, wherein the first verify operation includes first even sensing and second even sensing on even-numbered bit lines, and first odd sensing and second odd sensing on odd-numbered bit lines.

Abstract: A storage system that can achieve a cryptographic operation circuit that supports multiple types of cryptographic operation formats. The cryptographic operation circuit is provided that encrypts data according to the format determined by the processor based on a request by the host terminal for writing the data into the storage device, and decrypts the encrypted data on the data stored in the storage device according to the format determined by the processor based on a request by the host terminal for reading the data from the storage device.