Patents Examined by Khoa D Doan
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Patent number: 11941298Abstract: A host system initiates an abort of a command that has been placed into a submission queue (SQ) of the host system. The host system identifies at least one of a first outcome and a second outcome. When the first outcome indicates that the command is not completed and the second outcome indicates that the SQ entry has been fetched from the SQ, the host system sends an abort request to a storage device, and issues a cleanup request to direct the host controller to reclaim host hardware resources allocated to the command. The host system adds a completion queue (CQ) entry to a CQ and sets an overall command status (OCS) value of the CQ entry based on at least one of the first outcome and the second outcome.Type: GrantFiled: April 19, 2022Date of Patent: March 26, 2024Assignee: MediaTek Inc.Inventors: Chih-Chieh Chou, Chia-Chun Wang, Liang-Yen Wang, Chin Chin Cheng, Szu-Chi Liu
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Patent number: 11934704Abstract: Various devices, such as storage devices or systems are configured to efficiently manage and determine control table sets. Such a device may include a processor, a memory array including a plurality of memory devices which include a plurality of control table sets stored in a plurality of regions, and a control table set determination logic configured to: receive a command from a host device associated with logical to physical address mapping updates, determine a control table set of the plurality of control table sets associated with the command, determine a region of the plurality of regions associated with the determined control table set, determine a position in the control table set in the determined region associated with the command, generate additional control table sets upon a first determination that the position is not vacant, and store the command in the generated additional control table sets.Type: GrantFiled: September 27, 2022Date of Patent: March 19, 2024Assignee: Western Digital Technologies, Inc.Inventors: Pavithra P, Ashish Kumar
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Patent number: 11934660Abstract: Embodiments are directed to tiered data store with persistent layers. A write tier in the file system for storing in a file system. A value for a performance metric that corresponds to write requests to the file system may be predicted based on characteristics of the write requests such that the performance metric may be determined based on a plurality of interactions with the write tier. The predicted value that exceeds a threshold value of the performance metric may be employed to cause performance of further actions, including: queuing a portion of the write requests in a memory buffer based on the predicted value and the threshold value; combining the queued portion of the write requests into s; storing the data segments in the write tier such that a measured value of the performance metric may be less than the threshold value.Type: GrantFiled: November 7, 2023Date of Patent: March 19, 2024Assignee: Qumulo, Inc.Inventors: Matthew Christopher McMullan, Aaron James Passey, Jonathan Michael MacLaren, Yuxi Bai, Thomas Gregory Rothschilds, Michael Anthony Chmiel, Tyler Morrison Moody, Pathirat Kosakanchit, Rowan Arthur Phipps
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Patent number: 11922020Abstract: A read-disturb-based read temperature information persistence system includes a storage device coupled to a host subsystem. The storage device receives a first instruction from the host subsystem to write first data to the storage device, writes the first data to a first block in the storage device, and determines first read temperature(s) for the first data based on first read disturb information associated with the first block in the storage device. When a second instruction is received from the host subsystem to write second data to the storage device that is an updated version of the first data, the storage device identifies the first read temperature(s) determined for the first data in the first block in the storage device, and writes the second data and a first read temperature indication of the at least one first read temperature to a second block in the storage device.Type: GrantFiled: January 20, 2022Date of Patent: March 5, 2024Assignee: Dell Products L.P.Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
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Patent number: 11922036Abstract: Host data stream assignment with space-leveling across storage block containers. In one example, a data storage device including an electronic processor that, when executing a space-leveling scheme, is configured to receive a first host data stream, store the first host data stream in a block container assignment queue (BCAQ), detect a next storage block container switching event, responsive to detecting the next storage block container switching event, randomly select a location of the BCAQ, responsive to randomly selecting the location of the BCAQ, assign a second host data stream located at the location of the BCAQ that is selected to a storage block container of a memory, and control the memory to store the second host data stream in the storage block container that is assigned.Type: GrantFiled: May 12, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11921664Abstract: A storage device includes NVM package and a controller connected to the NVM package through a channel and controlling operation of the NVM package. The NVM package includes an interface chip, first NVM devices connected to the interface chip through a first internal channel and second NVM devices connected to the interface chip through a second internal channel. The interface chip selects the first internal channel in response to an operation request received from the controller and connects the first internal channel to the channel. The interface chip also determines whether retraining is necessary in relation to the second internal channel and transmits a retraining request to the controller when retraining is necessary.Type: GrantFiled: December 8, 2022Date of Patent: March 5, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Tongsung Kim, Jangwoo Lee, Seonkyoo Lee, Chiweon Yoon, Jeongdon Ihm
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Patent number: 11922019Abstract: A storage device read-disturb-based block read temperature utilization system includes a storage device chassis housing a storage subsystem. A local read temperature utilization subsystem in the storage device chassis determines that data in a first block in the storage subsystem should be moved and, in response determines read disturb information for the first block and uses it to identify relative read temperatures for a plurality of rows in the first block in the storage subsystem. The local read temperature utilization system then moves the data from the first block in the storage subsystem to at least one second block in the storage subsystem based on the relative read temperatures identified for the plurality of rows in the first block in the storage subsystem.Type: GrantFiled: January 20, 2022Date of Patent: March 5, 2024Assignee: Dell Products L.P.Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
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Patent number: 11921641Abstract: A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using a compacted L2P having an erase-block granularity. For a host logical address, the compacted L2P table only has the physical address of the corresponding erase block, which provides a first part of the pertinent physical address. A controller of the data storage device calculates a second part of the pertinent physical address based on the superblock layout employed in the device and further based on the sequential write requirement to the superblocks. The controller then obtains the full physical address corresponding to the host logical address by combining the first and second parts. The erase-block granularity of the compacted L2P table enables the full L2P table of the device to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.Type: GrantFiled: August 31, 2022Date of Patent: March 5, 2024Assignee: Western Digital Technologies, Inc.Inventors: Avinash Muthya Narahari, Rajthilak Dasarathan
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Patent number: 11907550Abstract: A method for dynamically assigning memory bandwidth to multiple processor units, which are connected via a data connection to a shared memory unit. In an initialization phase, each of the multiple processor units are assigned an initial value of a usable memory bandwidth, and a permissible range for a mean usage of the memory bandwidth is determined. Subsequently, the assigned memory bandwidths are checked repeatedly and adjusted if needed, a present value of a mean usage of the memory bandwidth by the multiple processor units being determined, and, if this present value is outside the permissible range, the values of the usable memory bandwidth are adjusted for at least a part of the multiple processor units.Type: GrantFiled: November 22, 2021Date of Patent: February 20, 2024Assignee: ROBERT BOSCH GMBHInventors: Ahsan Saeed, Dakshina Narahari Dasari, Falk Rehm, Michael Pressler
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Patent number: 11907533Abstract: An archiving apparatus that realizes high-speed seek processes and the like by setting a logical object table for each container file with a predetermined size, and closing the container file under a predetermined condition is provided. A data processing section that executes control of access to a recording medium generates a logical object table for managing a container file including logical objects which are recorded data units, and records the logical object table on a memory. In a case where a prescribed condition is satisfied, for example, the container file size has become equal to or larger than a prescribed end reference value, and so on, while a process on the container file is being executed, the logical object table is read out from the memory, and recorded on the recording medium, and the container file is closed.Type: GrantFiled: November 21, 2019Date of Patent: February 20, 2024Assignee: SONY GROUP CORPORATIONInventors: Hisao Tanaka, Tomotaka Kuraoka
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Patent number: 11907532Abstract: An initial drive cluster of G drives with G subdivisions is represented by a G*G drive matrix, where G equals the number of data and parity members in the RAID level implemented on the drive cluster. A corresponding G×G overlay matrix is created in which a value at row R, column C equals a remainder of (R+C?2) divided by G, such that there are G distinct values in a range of 0 to G?1. Responsive to addition of N new drives to the drive cluster, the N new drives are added to the drive matrix and the overlay matrix is used to select and relocate RAID members within the drive matrix so that new RAID groups can be created.Type: GrantFiled: November 10, 2022Date of Patent: February 20, 2024Assignee: Dell Products L.P.Inventor: Kuolin Hua
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Patent number: 11899970Abstract: A memory device includes; a first memory of first type, a second memory of second type different from the first type, and a memory controller. The memory controller receives an access request and workload information related to work of an external processor, processes the access request using the workload information, and accesses at least one of the first memory and the second memory in response to the access request.Type: GrantFiled: May 11, 2022Date of Patent: February 13, 2024Inventors: Wonseb Jeong, Hee Hyun Nam, Younggeon Yoo, Jeongho Lee, Younho Jeon, Ipoom Jeong, Chanho Yoon
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Patent number: 11899587Abstract: Systems and methods for object-based data storage are provided. There may be a read/write cache configured to cache objects to be written to an object-based data storage. A document in the read/write cache may have a lock state set to unlocked, thereby allowing the document to be deleted. Or, the document in the read/write cache may have a lock state set to locked, thereby preventing deletion of the document.Type: GrantFiled: July 18, 2022Date of Patent: February 13, 2024Assignee: RELATIVITY ODA LLCInventors: Jeffrey Hibser, Mohammad Amer Ghazal, Steven Engelhardt, Michael R. Gayeski, Brandon Michelsen, Ankit Khandelwal, Ranga Sankar, Robert A. Skinner
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Proactively biasing parameters of data storage device based on spatial position in storage enclosure
Patent number: 11880594Abstract: Disclosed are systems and methods for proactively, instead of reactively, biasing parameters of a data storage device based on a spatial position in a storage enclosure. The method includes obtaining a spatial position for the data storage device in a storage enclosure. The method also includes proactively biasing one or more parameters for controlling the device memory, based on the spatial position. The spatial position has a corresponding thermal profile that is predetermined.Type: GrantFiled: June 14, 2022Date of Patent: January 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Ramanathan Muthiah, Sridhar Sabesan, Dinesh Babu, Pavan Gururaj -
Patent number: 11880604Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.Type: GrantFiled: May 12, 2022Date of Patent: January 23, 2024Assignee: Western Digital Technologies, Inc.Inventors: Oleg Kragel, Vijay Sivasankaran, Mikhail Palityka, Lawrence Vazhapully Jacob
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Patent number: 11880571Abstract: The present disclosure relates to a method for accessing an array of memory cells, comprising the steps of storing user data in a plurality of memory cells of a memory array, storing, in a counter associated to the array of memory cells, count data corresponding to a number of bits in the user data having a predetermined first logic value, applying a read voltage to the memory cells to read the user data stored in the array of memory cells, applying the read voltage to the cells of the counter to read the count data stored in the counter and to provide a target value corresponding to the number of bits in the user data having the first logic value, wherein, during the application of the read voltage, the count data are read simultaneously to the user data in such a way that the target value is provided during the reading of the user data, and based on the target value of the counter, stopping the application of the read voltage when the number of bits in the user data having the first logic value correspondsType: GrantFiled: May 13, 2020Date of Patent: January 23, 2024Assignee: Micron Technology, Inc.Inventors: Riccardo Muzzetto, Ferdinando Bedeschi, Umberto di Vincenzo
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Patent number: 11875048Abstract: Provided is a memory management system based on a non-uniform memory access, which includes: a first persistent memory disposed in a first node; a second persistent memory disposed in a second node physically distinguished from the first node; a first journaling process disposed in the first persistent memory; and a second journaling process disposed in the second persistent memory.Type: GrantFiled: June 24, 2022Date of Patent: January 16, 2024Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Eui Seong Seo, Hyun Woo Ahn, Jong Seok Kim
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Patent number: 11868644Abstract: In one set of embodiments, a hardware module of a computer system can receive a stream of addresses corresponding to memory units being accessed by a central processing unit (CPU) of the computer system. The hardware module can further generate a frequency estimate for each address in the stream of addresses, the frequency estimate being indicative of a number of times a memory unit identified by the address has been accessed by the CPU, and can determine, based on the generated frequency estimates, a set of n most frequently accessed memory units.Type: GrantFiled: July 21, 2022Date of Patent: January 9, 2024Assignee: VMWARE, INC.Inventors: Andreas Georg Nowatzyk, Isam Wadih Akkawi, Pratap Subrahmanyam, Adarsh Seethanadi Nayak, Nishchay Dua
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Patent number: 11861197Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.Type: GrantFiled: December 10, 2021Date of Patent: January 2, 2024Assignee: Kioxia CorporationInventors: Yuki Sasaki, Shinichi Kanno
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Patent number: 11853612Abstract: A storage system includes two or more data storage devices and a controller coupled to the two or more data storage devices. Each data storage device of the two or more data storage devices includes zoned namespace (ZNS) architecture. The controller is configured to collect thermal statistics for each data storage device of the two or more data storage devices, analyze the collected thermal statistics, and designate a zone by selecting one or more dies within at least one data storage device of the two or more data storage devices based on the analyzed collected thermal statistics. The data storage device includes a memory device having a plurality of dies and a controller coupled to the memory device. The controller is configured to collect thermal statistics for each die of the plurality of dies, analyze the collected statistics, and allocate one or more dies to form a zone.Type: GrantFiled: April 6, 2022Date of Patent: December 26, 2023Assignee: Western Digital Technologies, Inc.Inventors: Avichay Haim Hodes, Judah Gamliel Hahn, Alexander Bazarsky