Abstract: A method for performing data access management of a memory device with aid of randomness-property control and associated apparatus are provided. The method may include: receiving a plurality of host commands from a host device and performing data access on the NV memory according to the plurality of host commands, for example, in response to at least one host write command, programming data into at least one single level cell (SLC) block to be first stored data corresponding to a data reception stage; and performing a seed-aware garbage collection (GC) procedure to collect valid data among the first stored data of the at least one SLC block into at least one non-SLC block to be second stored data corresponding to a data storage stage, for example, performing a randomness-property checking operation on multiple seeds to selectively determine respective data of multiple pages within the SLC block as target data.

Abstract: According to one embodiment, a memory system includes an array of memory cells that store two or more bits of data each, and a memory controller to control writing data into the memory cells and reading from the memory cells. When a first command is received from a host, the memory controller reads data designated by the first command from the array and then rewrites the read data back into the array using a writing method in which a lower number of bits per memory cell is written than the originally stored manner of the read data. When a read command designating the rewritten data is received from the host, the memory controller reads from the array and transfers it to the host.

Abstract: Read Fused Groups with uniform resource allocation. In one example, a data storage device including an electronic processor that, when executing the Uniform Read Fused Group scheme, is configured to receive information indicating each zone of a plurality of Zone Namespace (ZNS) zones is assigned to one of a plurality of Read Fused Groups (RFGs), assign a portion of a plurality of resources of a memory to the plurality of ZNS zones, control all of the plurality of concurrency units to process a first resource of the plurality of resources assigned to a first Read Fused Group (RFG) of the plurality of RFGs. The first resource is assigned to a first zone of the plurality of ZNS zones, the first zone is assigned to the first RFG, and the electronic processor is one of the plurality concurrency units.

Abstract: A data storage device and method for providing a temperature-driven variable storage capacity point are provided. In one embodiment, the data storage device determines that a temperature of the memory exceeds a threshold that triggers a decrease in performance of the data storage device; informs a host in communication with the data storage device that the temperature of the memory exceeds the threshold; receives an instruction from the host to avoid the decrease in the performance of the data storage device by reducing an effective capacity of the memory for an amount of time; and reduces the effective capacity of the memory for at least part of the amount of time by foregoing a background operation that maintains or increases the effective capacity of the memory. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A prefetch unit generates a prefetch address in response to an address associated with a memory read request received from the first or second cache. The prefetch unit includes a prefetch buffer that is arranged to store the prefetch address in an address buffer of a selected slot of the prefetch buffer, where each slot of the prefetch unit includes a buffer for storing a prefetch address, and two sub-slots. Each sub-slot includes a data buffer for storing data that is prefetched using the prefetch address stored in the slot, and one of the two sub-slots of the slot is selected in response to a portion of the generated prefetch address. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

Abstract: A data reading/writing circuit includes a controller and a memory. The memory is configured to decode an instruction based on a first clock signal from the controller and to sample data based on a second clock signal from the controller. The memory includes first and second storage modules, and a mode register that stores a second synchronization parameter, and a second delay circuit is disposed in the second storage module. In reading/writing data on the first storage module, the controller is configured to synchronize the first and second clock signals using a first synchronization parameter. In reading/writing data on the second storage module, the controller is configured to perform first synchronization on the first and second clock signals using the first synchronization parameter, and the memory is configured to perform second synchronization on the first and second clock signals using the second delay circuit and the second synchronization parameter.

Abstract: Methods, systems, and devices for memory can include techniques for identifying first quantities of write counts for a first plurality of super management units (SMUs) in a mapped region of a memory sub-system, identifying, by a hardware component of the memory sub-system, a first SMU of the first plurality that includes a fewest quantity of write counts of the first quantity of write counts, and performing a wear-leveling operation based at least in part on a first quantity of write counts of the first SMU of the first plurality in the mapped region being less than a second quantity of writes counts of a second SMU of a second plurality of SMUs in an unmapped region of the memory sub-system.

Abstract: A storage system includes a master storage device for storing data based on a RAID level determined by a host, a slave storage device for storing the data according to a command distributed from the master storage device, and a controller hub for coupling the slave storage device to the master storage device, wherein the master storage device is further configured to transfer the command to the slave storage device through the controller hub when the master storage device receives a command processing request from the host, transmit a complete queue (CQ) to the host when operations of the master storage device and the slave storage device are completed in response to the command processing request, and request a host to allocate a capacity to each function in the master storage device and the at least one of the plurality of slave storage devices based on a reference capacity.

Abstract: According to one embodiment, a memory system includes first, second, and third controllers. The first/second controller sets a first/second link to an operating or low power consumption state. The third controller sends a busy signal to the first and second controllers when transfer of a packet via the first or second link is predicted. When the first link is in the low power consumption state and a packet has not been received via the first link, the first link is maintained in the low power consumption state by disabling the busy signal. When the first link is in the operating state and a packet has not been received via the first link, the first link is transitioned to the low power consumption state upon absence of packets transferred via the first link for a first period of time, by disabling the busy signal.

Abstract: Logic may store data structures for two or more processors in memory such as cache, system management memory, protected memory, or other memory. Logic may compress the data structures to be stored in the memory. Logic may determine a reference data structure, store the reference data structure in the memory, determine a difference between a data structure for a second processor and the reference data structure, and store the difference in the memory. Logic may store the difference in the memory within a data structure such as a linked list or a bitmap. Logic may decompress the difference by combining the difference with the reference data structure. Logic may expand the useable data region to include cache in the two or more processors. Logic may instruct two or more processors to store their processor data structures in their respective caches and perform initialization with the processor data structures.

Abstract: A system for file system data access can include memory devices including a non-volatile memory device, as well as a processing device, operatively coupled with the memory devices to perform operations including receiving a file system (FS) write command and determining whether a write count of a physical super management unit (PSMU) of the non-volatile memory device satisfies a threshold criterion. The operations can include, recording a change of a super management unit (SMU) mapping for FS data of an FS mapping table, where the FS mapping table is a portion of a logical-to-physical (L2P) mapping table and performing a move of SMU data corresponding to the change of the SMU mapping. They can also include creating a backup copy of the FS mapping table on the non-volatile memory device, and restoring the FS mapping table from the backup copy of the FS mapping table.

Abstract: Methods, systems, and devices for using page line filler data are described. In some examples, a memory system may store data within a write buffer of the memory system. The memory system may initiate an operation to transfer the write buffer data to a memory device, for example, due to a command to perform a memory management operation (e.g., cache synchronization, context switching, or the like) from a host system. In some examples, a quantity of write buffer data may fail to satisfy a data size threshold. Thus, the memory system may aggregate the data in the write buffer with valid data from a block of the memory device associated with garbage collection. The memory system may aggregate the write buffer data with the garbage collection data until the aggregated data satisfies the data size threshold. The memory system may then write the aggregated data to the memory device.

Abstract: According to one embodiment, an information processing device includes a processor. The processor receives a signal for requesting each of a plurality of storage devices to execute a first process. Based on the received signal, the processor transmits a first command, corresponding to the first process, to each of the plurality of storage devices using a plurality of identifiers relating to the plurality of storage devices, respectively.

Abstract: A system including an array of processing elements, a plurality of periphery crossbars and a plurality of storage components is described. The array of processing elements is interconnected in a grid via a network on an integrated circuit. The periphery crossbars are connected to a plurality of edges of the array of processing elements. The storage components are connected to the periphery crossbars.

Abstract: Methods, systems, and devices related to operating a memory array are described. A system may include a memory device and a host device. A memory device may indicate information about a temperature of the memory device, which may include sending an indication to the host device after receiving a signal that initializes the operation of the memory device or storing an indication, for example in a register, about the temperature of the memory device. The information may include an indication that a temperature of the memory device or a rate of change of the temperature of the memory device has satisfied a threshold. Operation of the memory device, or the host device, or both may be modified based on the information about the temperature of the memory device. Operational modifications may include delaying a sending or processing of memory commands until the threshold is satisfied.

Abstract: A metadata volume bitmap data conflict processing method. When the space allocation of a metadata volume encounters conflicts of 0-to-1 and 1-to-0, a conflict bit is set to be 1, so that when a garbage collector periodically performs space collection processing, data loss when data is overwritten due to collection of the bit to space corresponding to the bit in the case that I bit is detected to be 0 at one end may be avoided; when a conflict happens, conflict bits are both set to be 1, so that the conflict bits may be prevented from being allocated again, the space is prevented from being repeatedly allocated and repeatedly written and thus the data loss due to data overwriting is avoided, and after the garbage collection collects the conflict bits, continuous allocation may be performed, thereby implementing the repeated utilization of the conflict bits.

Abstract: A storage device includes a buffer memory configured to temporarily store data; a plurality of nonvolatile memory devices; a storage controller circuit configured to generate buffer memory status information by monitoring a status of the buffer memory and operating in a congestion control mode of setting a buffer memory data transmission authority of a nonvolatile memory based on the generated buffer memory status information; and a first interface circuit configured to communicate with the storage controller circuit and the plurality of nonvolatile memory devices, wherein the first interface circuit is connected to a network based on an Ethernet interface.

Abstract: An example method includes transferring, for each of a plurality of snapshots of a source virtual storage volume mounted at a first compute node, at least a portion of a plurality of data blocks for each of the snapshots to a target virtual storage volume at a second compute node; and after the data blocks are transferred, resynchronizing the target virtual storage volume with the source virtual storage volume.

Abstract: A storage device may include a plurality of memory devices and a memory controller in communication with the plurality of memory devices through a plurality of channels. The memory controller may select candidate channels to be activated among the plurality of channels, determine a threshold number of channel activation based on a number of channels in an active state before a first time point, and activate one or more target channels among the candidate channels so that a number of the target channels to be activated at the first time point is within the threshold number.

Abstract: An information handling system may include a processor and a management controller communicatively coupled to the processor. The management controller may be configured to, in response to an encrypted storage resource being coupled to the information handling system: transmitting a request to at least one other management controller for an encryption key associated with the encrypted storage resource; receiving a response from the at least one other management controller, the response including the encryption key associated with the encrypted storage resource; and unlocking the encrypted storage resource with the received encryption key.