Abstract: An embodiment of the present invention provides a display device including a substrate including a display area, and a peripheral area outside the display area and including a bending area, a first conductive layer including a first signal wire over the substrate, a first insulating layer over the first conductive layer, a second insulating layer in a different layer from the first insulating layer, overlapping the bending area, and having a first edge positioned around the bending area, and a protector over the second insulating layer, wherein the first signal wire is in the peripheral area, crosses the first edge of the second insulating layer, does not overlap the bending area, and includes a first portion not covered by the second insulating layer, and wherein the protector overlaps at least a portion of the first portion, and has an edge that is parallel with an edge of the first portion.

Abstract: A power converter circuit includes an inductor and rectifier circuit having an inductor connected in series with an electronic switch, and a rectifier circuit, and a controller for generating a drive signal for driving the electronic switch. The electronic switch has drain, source and gate nodes, drift and compensation cells each including a drift region of a first doping type and a compensation region of a second doping type, and a control structure connected between the drift region of each of the drift and compensation cells and the source node. Each drift region is coupled to the drain node and each compensation region cells is coupled to the source node. A first type doping concentration N1 of the drift region is higher than a first doping level L1, and a second type doping concentration N2 of the compensation region is higher than a second doping level L2.

Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.

Abstract: An active matrix substrate (100) according to an embodiment of the present invention has a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix pattern, and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10) supported on the substrate and including a crystalline silicon semiconductor layer (11), and a second TFT (20) supported on the substrate and including an oxide semiconductor layer (21). The first TFT and the second TFT each have a top gate structure. The oxide semiconductor layer is located below the crystalline silicon semiconductor layer.

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.

Abstract: The present disclosure provides a display panel and a fabrication method thereof and a display device. The display panel includes a first substrate and a second substrate, which are aligned and assembled to form a cell, and a sealant sandwiched between the first substrate and the second substrate, wherein a hollow structure is arranged in at least one of a first surface layer of the first substrate facing the second substrate and a second surface layer of the second substrate facing the first substrate, and wherein a portion of the sealant is embedded in the hollow structure.

Abstract: This disclosure relates to a display and a method of fabricating the display. According to some embodiments, the display may comprise: an encapsulation sidewall; at least one isolation column adjacent to the encapsulation sidewall; and a processing module coupled with the at least one isolation column, configured to apply a voltage signal to the at least one isolation column according to a height of the encapsulation sidewall, such that the at least one isolation column deforms.

Abstract: Disclosed are a backplane substrate, which is devised to attain circuit characteristics for realizing sufficient gradation even in smaller pixels of a super-high-resolution structure, a manufacturing method for the same, and an organic light-emitting display device using the same, inn the backplane substrate, a driving thin-film transistor has a stack structure different from that of other thin-film transistors so that only the S-factor of the driving thin-film transistor is increased.

Abstract: An organic light emitting diode display device includes a substrate, a protection layer on the substrate, the protection layer including a trench pattern and a recessed portion, a first electrode on the protection layer, a pixel defining layer on the protection layer, the pixel defining layer defining an opening that exposes at least a part of the first electrode, an organic light emitting layer on the first electrode, and a second electrode on the organic light emitting layer. The recessed portion overlaps the opening and is spaced apart from an edge of the opening in a plan view. The trench pattern includes a plurality of trenches extending along a first direction. Each trench of the plurality of trenches is spaced apart from the first electrode in a plan view and has a concave cross-section.

Abstract: The present invention provides a high voltage ESD protection device including a P-type substrate; a first NWELL region located on the left of the upper part of the P-type substrate; an NP contact region located on the upper part of the first NWELL region; an N+ contact region located on the right of the upper part of the P-type substrate apart from the first NWELL region; a P+ contact region tangential to the right side of the N+ contact region; a NTOP layer arranged on the right of the NP contact region inside the first NWELL region. The NP contact region is connected to a metal piece to form a metal anode. The N+ contact region and the P+ contact region are connected by a metal piece to form a metal cathode.

Abstract: A novel light-emitting element is provided. Alternatively, a novel light-emitting element which can achieve both high efficiency and a long lifetime is provided. The light-emitting element includes a light-emitting layer between a pair of electrodes. The light-emitting element includes a first light-emitting layer and a second light-emitting layer. The first light-emitting layer includes a fluorescent material. The second light-emitting layer includes a phosphorescent material. A difference in peak value between a first emission spectrum of light from the first light-emitting layer and a second emission spectrum of light from the second light-emitting layer is 30 nm or less.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.

Abstract: Aspects generally relate to adjusting, or lowering, the Q of an inductor. In one embodiment, an integrated circuit includes an inductor and a conductive closed ring inside a periphery of the inductor. In another embodiment, there can be a plurality of closed rings inside the periphery of the inductor. The conductive closed rings are magnetically coupled to the inductor to adjust the Q.

Abstract: A display element includes: a base substrate; a metal layer on the base substrate; a passivation film on the base substrate and covering the metal layer; an electrode on the passivation film and at least partially overlapping the metal layer; and a pixel defining film on the passivation film. The pixel defining film has an opening at least partially exposing the electrode, and portions of the electrode offset from the metal layer are below a portion of the electrode overlapping the metal layer such that trenches are defined in the opening.

Abstract: A Schottky diode includes a cathode terminal in a high voltage region of a semiconductor die, an anode terminal in a low voltage region of the semiconductor die, where the anode terminal and the cathode terminal are separated by a junction isolation termination situated between the high voltage region and the low voltage region. The Schottky diode includes a junction barrier Schottky diode or a trench metal-oxide-semiconductor (MOS) Schottky diode. The junction isolation termination includes pzener rings. The semiconductor die includes a substrate of a first conductivity type, an epitaxial layer of a second conductivity type situated on the substrate, a well region of the second conductivity type situated in the epitaxial layer in the high voltage region, and coupled to the cathode terminal, a Schottky barrier situated on the epitaxial layer in the low voltage region, and coupled to the anode terminal.

Abstract: The semiconductor device is provided with a plurality of switching elements connected in parallel to each other, and a plurality of recirculation element connected in parallel to the aforementioned plurality of switching elements. An emitter electrode serves as a reference potential of the aforementioned plurality of switching elements and an anode electrode serves as a reference potential of the aforementioned plurality of recirculation elements are electrically connected by the same plate-like member consisting of a conductive material. The aforementioned switching elements and the aforementioned recirculation elements which are connected in parallel on the lowest potential side are constituted so that the distance from the emitter terminal connected to the aforementioned emitter electrode to the aforementioned recirculation element becomes no greater than the distance from the aforementioned emitter terminal.

Abstract: Semiconductor memory devices are provided. A semiconductor memory device includes a cell array region including stacked structures and a word line cut region that extends between the stacked structures. Moreover, the semiconductor memory device includes a peripheral circuit region in a stack with the cell array region and including a support pattern.

Abstract: Disclosed is a photodetector which includes, in series along a stacking direction: a first layer forming a substrate of a first semiconductor material; a second layer forming a photoabsorbent layer of a second semiconductor material having a second gap; a third layer forming a barrier layer of a third semiconductor material; and a fourth layer forming a window layer of a fourth semiconductor material, the first material, the third material and the fourth material each having a gap larger than the second gap, the fourth material being n-doped or non-doped and the third material being non-doped or lightly p-doped when the second material is n-doped, and the fourth material being p-doped or non-doped and the third material being non-doped or lightly n-doped when the second material is p-doped.

Abstract: A semiconductor device includes a substrate, a plurality of channel layers stacked on the substrate, a gate electrode surrounding the plurality of channel layers, and embedded source/drain layers on opposing sides of the gate electrode. The embedded source/drain layers each have a first region and a second region on the first region. The second region has a plurality of layers having different compositions.

Abstract: In one exemplary aspect, a method comprises providing a semiconductor structure having a substrate, one or more first dielectric layers over the substrate, a first metal plug in the one or more first dielectric layers, and one or more second dielectric layers over the one or more first dielectric layers and the first metal plug. The method further comprises etching a via hole into the one or more second dielectric layers to expose the first metal plug, etching a top surface of the first metal plug to create a recess thereon, and applying a metal corrosion protectant comprising a metal corrosion inhibitor to the top surface of the first metal plug.