Abstract: A bonding structure for a flexible screen and a manufacturing method are provided a flexible screen and a chip mounted on a surface of the flexible screen are arranged on the bonding structure for the flexible screen, and a bonding area for bonding the chip is arranged on the flexible screen, and a flexible protective layer is coated in the bonding area, and the flexible protective layer surrounds around the chip. Compared with the prior art, by forming the flexible protective layer with different hardness around the chip, the stress generated around the chip during the peeling-off are greatly dispersed, a stress gradient is formed, the stress concentration at the position closely adjacent to the periphery of the chip is avoided, the risk of the circuits around the chip being pulled broken can be reduced, and the peeling-off yield of the flexible screen can be finally increased.

Abstract: An organic light-emitting display device including a partition wall is provided. The organic light-emitting display device includes a first bank insulating layer covering an edge of a lower electro and a second bank insulating layer supporting the partition wall. The second bank insulating layer is completely spaced apart from the first bank insulating layer. The first bank insulating layer facing the second bank insulating layer is completely covered by an upper electrode which is disposed on a portion of the lower electrode exposed by the first bank insulating layer.

Abstract: A light-emitting apparatus includes: a solid-state light source; and a wavelength convertor. The solid-state light source emits first light including green light with a peak wavelength in a range of 480 to 550 nm, inclusive. The wavelength convertor contains a red phosphor including Ce as a luminescent center. The red phosphor is excited by at least part of the green light to emit second light. The second light has a spectrum with a peak wavelength in a range of 600 to 700 nm, inclusive. The red phosphor contains a nitride or an oxynitride as a host material.

Abstract: A display device includes: a display panel; and a color conversion panel overlapping the display panel, wherein the color conversion panel includes a red color conversion layer and a green color conversion layer including a semiconductor nanocrystal, and a transmissive layer; a red color filter overlapping the red color conversion layer; a green color filter overlapping the green color conversion layer; and a blue color filter overlapping the transmissive layer and a light blocking member, and the light blocking member includes at least one of a blue dye and a blue pigment.

Abstract: A display substrate and an OLED display device, the display substrate including a water absorbing structure disposed on the display substrate that is configured to be capable of absorbing moisture in the display substrate. In the embodiments of the present invention, by providing a water absorbing structure in the display substrate, it is possible to protect the organic luminescent unit from moisture released in the process of manufacturing and operating the display substrate, enhance the performance of the OLED display device and prolong the service life of the OLED display device.

Abstract: The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.

Abstract: A semiconductor device includes gate electrodes stacked along a direction perpendicular to an upper surface of a substrate, the gate electrodes extending to different lengths in a first direction, and each gate electrode including subgate electrodes spaced apart from each other in a second direction perpendicular to the first direction, and gate connection portions connecting subgate electrodes of a same gate electrode of the gate electrodes to each other, channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, and dummy channels extending through the gate electrodes perpendicularly to the upper surface of the substrate, the dummy channels including first dummy channels arranged in rows and columns, and second dummy channels arranged between the first dummy channels in a region including the gate connection portions.

Abstract: The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.

Abstract: An imaging device includes: pixels arranged one-dimensionally or two-dimensionally, each of the pixels including an electrode that is electrically connected to the other pixels, a charge capturing unit that is separated from the other pixels, and a photoelectric conversion layer that is located between the electrode and the charge capturing unit, the photoelectric conversion layer being continuous among the pixels. The photoelectric conversion layer contains semiconductor carbon nanotubes, and one of a first substance and a second substance, the first substance having an electron affinity larger than that of the semiconducting carbon nanotubes, the second substance having a ionization energy smaller than that of the semiconductor carbon nanotubes.

Abstract: An organic light emitting diode comprises a hole transport layer, an emissive layer, and an electron transport layer. The hole transport layer and optionally the electron transport layer is made of a material having a refractive index having a specific anisotropy.

Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.

Abstract: A package structure includes a redistribution circuit structure, at least one semiconductor die, an insulating encapsulation, insulators, and metallic patterns. The at least one semiconductor die is located on and electrically connected to the redistribution circuit structure. The insulating encapsulation encapsulates the at least one semiconductor die and located on the redistribution circuit structure. The insulators are located on the redistribution circuit structure, wherein the insulators are separated and spaced apart from each other, wherein edges of each of the insulators are distant from edges of the at least one semiconductor die by an offset in a stacking direction of the redistribution circuit structure and the insulating encapsulation. Each of the metallic patterns is located on a respective one of the insulators.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin structure on a substrate; a first gate stack and a second gate stack formed on the fin structure; a dielectric material layer disposed on the first and second gate stacks, wherein the dielectric layer includes a first portion disposed on a sidewall of the first gate stack with a first thickness and a second portion disposed on a sidewall of the second gate stack with a second thickness greater than the first thickness; a first gate spacer disposed on the first portion of the dielectric material layer; and a second gate spacer disposed on the second portion of the dielectric material layer.

Abstract: A semiconductor device includes a semiconductor region having charge carriers of a first conductivity type, a transistor cell in the semiconductor region, and a semiconductor channel region in the transistor cell and having a first doping concentration of charge carriers of a second conductivity type. A semiconductor auxiliary region in the semiconductor region has a second doping concentration of charge carriers of the second conductivity type, which is at least 30% higher than the first doping concentration. A pn-junction between the semiconductor auxiliary region and the semiconductor region is positioned as deep or deeper in the semiconductor region as a pn-junction between the semiconductor channel region and the semiconductor region. The semiconductor auxiliary region is positioned closer to the semiconductor channel region than any other semiconductor region having charge carriers of the second conductivity type and that forms a further pn-junction with the semiconductor region.

Abstract: An image sensor includes a substrate including opposite first and second surfaces, first and second gates, on the first surface of the substrate, which each extend in a first direction, a first isolation layer in the substrate between the first and second gates and having a first width in a second direction crossing the first direction, a second isolation layer on the first isolation layer, in the substrate, and having a second width smaller than the first width in the second direction. The second isolation layer is closer to the second surface of the substrate than the first isolation layer. A vertical distance between the first isolation layer and the second isolation layer is ? or less of a height of the first isolation layer.

Abstract: The present application discloses an array substrate having a display area and a peripheral area. The array substrate includes a plurality of first thin film transistors respectively in a plurality of subpixels in the display area; and a plurality of second thin film transistors in the peripheral area, an oxygen content in active layers of the plurality of first thin film transistors being higher than that in active layers of the plurality of second thin film transistors.

Abstract: A thin film transistor array formed substrate including a gate electrode, a gate insulation layer, a source wiring structure including a source wiring and a source electrode, a drain electrode, a pixel electrode connected to the drain electrode, a semiconductor layer formed in a stripe shape having a longitudinal side extending in a direction that the source wiring extends, and a protection layer formed to cover an entire portion of the semiconductor layer. The source wiring structure has notch portions positioned in the direction that the source wiring extends such that the notch portions overlap with the gate electrode, the source wiring has a first portion having a first width where the notch portions are formed and a second portion having a second width larger than the first width where no notch portions are formed, and the source wiring has an opening in the second portion.

Abstract: A perpendicularly magnetized magnetic tunnel junction (p-MTJ) is disclosed wherein a free layer (FL) has a first interface with a MgO tunnel barrier, a second interface with a Mo or W Hk enhancing layer, and is comprised of FexCoyBz wherein x is 66-80, y is 5-9, z is 15-28, and (x+y+z)=100 to simultaneously provide a magnetoresistive ratio >100%, resistance x area product <5 ohm/?m2, switching voltage <0.15V (direct current), and sufficient Hk to ensure thermal stability to 400° C. annealing. The FL may further comprise one or more M elements such as O or N to give (FexCoyBz)wM100-w where w is >90 atomic %. Alternatively, the FL is a trilayer with a FeB layer contacting MgO to induce Hk at the first interface, a middle FeCoB layer for enhanced magnetoresistive ratio, and a Fe or FeB layer adjoining the Hk enhancing layer to increase thermal stability.

Abstract: The invention discloses an organic light-emitting display panel, an electronic device and a method for manufacturing the same. The organic light-emitting display panel includes: pixel regions on a substrate which emit light of various colors; each pixel region includes a first electrode, a light-emitting functional layer and a second electrode, one of the first electrode and the second electrode is light exit side electrode(s); an optical coupling layer is set on one side of the light exit side electrode far from the light-emitting functional layer; the refractive index of the optical coupling layer in the blue light wavelength region is 2 to 2.3; the difference between the refractive index of the optical coupling layer in the blue light wavelength region and that in the green light wavelength region is less than or equal to 0.2.

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.