Abstract: Embodiments provide a light emitting device package including a first lead frame and a second lead frame, a light emitting device electrically connected to each of the first lead frame and the second lead frame, the light emitting device having a first electrode pad asymmetrically formed on a top surface thereof, and a reflective member disposed around the light emitting device to reflect light emitted from the light emitting device. The reflective member is configured such that a standard deviation of tilts of a reflective surface of a first area, in which the first electrode pad is disposed, is greater than a standard deviation of tilts of a reflective surface of a second area opposite to the first area.

Abstract: A method for forming a thermoelectric element for use in a thermoelectric device comprises providing a mask adjacent to a substrate, the mask comprising a polymeric mixture, and bringing a template having a first pattern in contact with the mask to define a second pattern in the mask. The first pattern comprises one of holes and rods, and the second pattern comprises the other of holes and rods. Holes or rods of the second pattern expose portions of the substrate. Next, an etching layer is deposited adjacent to exposed portions of the substrate. The etching layer is configured to aid in etching the substrate. The substrate is subsequently etched with the aid of the etching layer.

Abstract: A red phosphor including the composition represented by the following general formula. (x?a)MgO.(a/2)Sc2O3.yMgF2.cCaF2.(1?b)GeO2.(b/2)Mt2O3:zMn4+ where x, y, z, a, b, and c satisfy 2.0?x?4.0, 0<y<1.5, 0<z<0.05, 0?a<0.5, 0<b<0.5, 0?c<1.5, and y+c<1.5, and Mt is at least one element selected from the group consisting of Al, Ga, and In.

Abstract: An organic light emitting diode display device includes: a substrate; a first electrode on the substrate; a hole transport layer on the first electrode; an organic light emitting layer on the hole transport layer; and a second electrode on the organic light emitting layer. The hole transport layer includes a hole transport layer composition including a compound represented by Chemical Formula 1, a compound represented by Chemical Formula 2, a compound represented by Chemical Formula 3, and a compound represented by Chemical Formula 4.

Abstract: A semiconductor device includes an insulating substrate including a substrate, a metal pattern formed on an upper surface of the substrate, and a metal film formed on a lower surface of the substrate, a semiconductor element fixed on the metal pattern, a case surrounding the metal pattern and having a contact portion maintained in contact with the upper surface of the substrate, and an adhesive with which the case and a portion of the upper surface of the substrate outside a portion maintained in contact with the contact portion are bonded together, wherein a plurality of through holes are formed in a peripheral portion of the case, the through holes extending vertically through the case, and wherein the metal film exists in at least part of a place right below the contact portion.

Abstract: A power conversion device includes a heat releasing heatsink, a printed circuit board provided on the heatsink and having a through hole and wires, a metal case having a depressed portion fitted in the through hole and mounted on a top of the heatsink, and a heat releasable insulating layer made of a ceramic material and disposed between a bottom of the depressed portion and a top portion of the heat sink. A power semiconductor element is mounted in the depressed portion and electrically connected to the wires of the printed circuit board.

Abstract: A strain relaxed buffer layer of a second semiconductor material and of a second lattice constant and containing misfit dislocation defects and threading dislocation defects is formed atop a surface of a first semiconductor material of a first lattice constant that differs from the second lattice constant. The surface of the first semiconductor material includes at least one recessed region and adjoining non-recessed regions. An anneal is then performed on the strain relaxed buffer layer to propagate and amass the misfit dislocation defects and threading dislocation defects at a sidewall of each of the non-recessed regions of the first semiconductor material.

Abstract: A mold release film, which is excellent in releasability and capable of suppressing contamination of a mold or a resin-encapsulation portion by the mold release film and forming a resin-encapsulation portion excellent in adhesion to an ink layer, is provided. The mold release film is disposed on a cavity surface of a mold, in which a semiconductor element is disposed and encapsulated with a curable resin to form a resin-encapsulation portion. The mold release film has a first surface in contact with the curable resin when the resin-encapsulation portion is formed, and a second surface in contact with the cavity surface. At least the first surface is made of a fluororesin. The mold release film has an F/Al ratio of from 0.2 to 4, or an F/(C+F+O) ratio of from 0.1 to 0.3. A process for producing a semiconductor package using the mold release film is also provided.

Abstract: In a surface light-emitting unit, a wiring board (60) includes, on its side on which a holding substrate (11) is located, an external-wire connecting portion (40). An opening (11h) is provided in the holding substrate (11). The wiring board (60) is disposed to cover the opening (11h) and allow the external-wire connecting portion (40) to be exposed, through the opening (11h), toward a surface of the holding substrate (11) opposite to the surface thereof on which the wiring board (60) is held. With an external wire connected to the external-wire connecting portion (40), a surface of the wiring board (60) located in the opening (11h) is sealed by a second sealing member.

Abstract: A light emitting diode includes an n-type semiconductor layer disposed on a substrate; a p-type semiconductor layer disposed on a portion of the n-type semiconductor layer; an active layer disposed between the n-type semiconductor layer and the p-type semiconductor layer and generating light through recombination of electrons and holes; an ohmic contact layer disposed on the p-type semiconductor layer and including an indium tin oxide (ITO) layer doped with a metal, a transparent conductive layer disposed on the ohmic contact layer to a different thickness than the ohmic contact layer and including an undoped ITO layer, and a reflective layer disposed on the transparent conductive layer and including an oxide layer. Accordingly, the light emitting diode exhibits excellent current-voltage characteristics through improvement in reliability and electrical conductivity of the ohmic contact layer while improving luminous efficacy through the reflective layer formed of an oxide.

Abstract: A method of bonding a plurality of die having first and second metal layers on a die surface to a board, comprising placing a first die onto a board comprising one of a ceramic or substrate board or metal lead frame having a solderable surface and placing the first die and the board into a reflow oven. The method includes reflowing at a first reflow temperature for a first period until the first metal board layer and at least one of the first and second metal die layers of the first die form an alloy to adhere the first die to the board. The newly formed alloy has a higher melting temperature than the first reflow temperature. Accordingly, additional die may be reflowed and attached to the board without causing the bonding of the first die to the board to fail if the same reflow temperature is used.

Abstract: There is provided a nanostructure semiconductor light emitting device including a base layer formed of a first conductivity-type semiconductor, a first insulating layer disposed on the base layer and having a plurality of first openings exposing partial regions of the base layer, a plurality of nanocores disposed in the exposed regions of the base layer and formed of the first conductivity-type semiconductor, an active layer disposed on surfaces of the plurality of nanocores positioned to be higher than the first insulating layer, a second insulating layer disposed on the first insulating layer and having a plurality of second openings surrounding the plurality of nanocores and the active layer disposed on the surfaces of the plurality of nanocores, and a second conductivity-type semiconductor layer disposed on the surface of the active layer positioned to be higher than the second insulating layer.

Abstract: A semiconductor device includes a stripe-shaped electrode structure that extends from a first surface into a semiconductor portion. The electrode structure includes a main portion and an end portion terminating the electrode structure. The main portion includes a field electrode and a first portion of a field dielectric separating the field electrode from the semiconductor portion. The end portion includes a filled section in which a second portion of the field dielectric extends from a first side of the electrode structure to an opposite second side. The filled section is narrower than the main portion and a length of the filled section along a longitudinal axis of the electrode structure is at least 150% of a first layer thickness of the first portion of the field dielectric.

Abstract: A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive line including a first conductive material, and a second conductive line including a second conductive material. A via connects the first conductive line to the second conductive line, wherein the via includes conductive via material, wherein the via material top surface is coated with a liner material, wherein the via is a bottomless via.

Abstract: Techniques for fabricating a memory device which has reduced neighboring word line interference, and a corresponding memory device. The memory device comprises a stack of alternating conductive and dielectric layers, where the conductive layers form word lines or control gates of memory cells. In one aspect, the memory device is provided with a reduced dielectric constant (k) in locations of a fringing electric field of the control gate. For example, portions of the dielectric layers can be replaced with a low-k material. One approach involves recessing the dielectric layer and providing a low-k material in the recess. Another approach involves doping a portion of the blocking oxide layer to reduce its dielectric constant. Another approach involves removing a portion of the blocking oxide layer. In another aspect, the memory device is provided with an increased dielectric constant adjacent to the control gates.

Abstract: An organic light emitting diode (OLED) display includes a substrate, OLEDs disposed on the substrate and separated from each other, pixel circuits, data lines extending in a first direction on the substrate and separated from each other in a second direction crossing the first direction, connecting lines neighboring the data lines and extending in the first direction, and a wire directly connecting one portion of one of the data lines to one portion of one of the connecting lines neighboring the one data line. Each pixel circuit includes a plurality of thin film transistors and each pixel circuit is connected to one of the OLEDs. The data lines and the connecting lines are connected to the pixel circuits, and one or more surfaces of the one portion of the one data line and the one portion of the one connecting line that contact the wire are curved.

Abstract: A semiconductor light-emitting element includes a substrate and a semiconductor stack portion provided on the substrate and having at least a first-conductivity-type semiconductor layer, a light-emitting layer, and a second-conductivity-type semiconductor layer. The substrate has a property to allow transmission of light from the light-emitting layer, and has a hexahedral shape including a first surface on which a semiconductor stack portion is provided, a second surface located opposite to the first surface, a pair of third surfaces orthogonal to the first surface and the second surface, and a pair of fourth surfaces orthogonal to the first surface and the second surface and different from the pair of third surfaces.

Abstract: An organic light-emitting display device includes an organic light-emitting element on a substrate, a metal substrate, and an encapsulation unit configured to seal the organic light-emitting element, and a structure in which a driving film is connected so as not to be protruded further than the substrate. A portion of the encapsulation unit is between the metal substrate and the driving film, and the portion of the encapsulation unit is configured to reduce damage to the driving film caused by the metal substrate. Thus, the organic light-emitting display device may realize a narrow bezel and also reduce a driving defect caused by damage to the driving film.

Abstract: Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure includes first gate insulating layer on the first fin-type active region to cover upper surface and both side surfaces of the first fin-type active region, first gate electrode on the first gate insulating layer and has first thickness in first direction perpendicular to upper surface of the substrate, and second gate electrode on the first gate electrode. The second gate structure includes second gate insulating layer on the second fin-type active region to cover upper surface and both side surfaces of the second fin-type active region, third gate insulating layer on the second gate insulating layer, third gate electrode on the third gate insulating layer and has second thickness different from the first thickness in the first direction, and fourth gate electrode on the third gate electrode.

Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.