Patents Examined by Kien Ly
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Patent number: 9559014Abstract: A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.Type: GrantFiled: November 24, 2015Date of Patent: January 31, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Veeraraghavan Basker, Kangguo Cheng, Theodorus Standaert, Junli Wang
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Patent number: 9553143Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.Type: GrantFiled: February 12, 2015Date of Patent: January 24, 2017Assignee: Vanguard International Semiconductor CorporationInventors: Shang-Hui Tu, Yu-Lung Chin, Shin-Cheng Lin
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Patent number: 9548428Abstract: A light emitting diode includes: a substrate of front and back main surfaces; a V-shaped groove, which has a reflecting surface, formed over front surface of the conductive substrate; a light-emitting epitaxial layer, the margin of which has its vertical projection between the bottom and the inner margin of the V-shaped groove, formed over the substrate, so that light emitted from the light-emitting epitaxial layer margin is incident to the mirror surface of the V-shaped groove and emits outwards. This structure can effectively improve extraction efficiency of device and control path of light at peripheral region of the light-emitting epitaxial layer.Type: GrantFiled: October 17, 2015Date of Patent: January 17, 2017Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Cuicui Sheng, Shuying Qiu, Chaoyu Wu, Ching-Shan Tao, Wenbi Cai
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Patent number: 9537057Abstract: A surface-mounted light-emitting device includes: a LED epitaxial structure having two opposite surfaces, wherein the first surface is a light-emitting surface; P and N electrode pads over the second surface of the epitaxial structure, which have sufficient thickness to support the LED epitaxial structure, and the P and N electrode pads have two opposite surfaces respectively, in which, the first surface is approximate to the LED epitaxial structure; an insulator between the P and N pads to prevent the P and N electrode pads from short circuit; and the P and N electrode pads are directly applied in the SMT package. Some embodiments allow structural changes compared with conventional SMT package type by directly mounting the chip over the supporting substrate through an electrode pad. In addition, soldering is followed after the chip process without package step, which is mainly applicable to flip-chip LED device.Type: GrantFiled: June 24, 2015Date of Patent: January 3, 2017Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Shaohua Huang, Xiaoqiang Zeng, Chih-Wei Chao
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Patent number: 9484330Abstract: A light-emitting device includes light-emitting units and an electrical connection layer. Each light-emitting unit includes a light-emitting stacking layer, a first electrode layer, an insulation layer, and a second electrode layer. The light-emitting stacking layer includes first and second-type doped semiconductor layers, an active layer, and a first inner opening passing through the second-type doped semiconductor layer and the active layer. The second electrode layer is close to and is electrically connected to the second-type doped semiconductor layer. The insulation layer is disposed on a sidewall of the first inner opening and forms a second inner opening. The first electrode layer is disposed in the second inner opening and electrically connected to the first-type doped semiconductor layer. The electrical connection layer is electrically connected to the first electrode layer of one of two adjacent light-emitting units and the second electrode layer of the other adjacent light-emitting unit.Type: GrantFiled: August 10, 2015Date of Patent: November 1, 2016Assignee: PlayNitride Inc.Inventor: Shao-Hua Huang
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Patent number: 9472712Abstract: According to one embodiment, a semiconductor light emitting device includes a semiconductor layer, an electrode pad, a first electrode, a second electrode and a layer. The semiconductor layer includes a first semiconductor layer, a second semiconductor layer, and a light emitting layer. The electrode pad is provided in adjacent to the semiconductor layer. The first electrode is connected to the electrode pad with one end, extends from the electrode pad, and is connected to the first semiconductor layer. The second electrode is connected to the second semiconductor layer. The layer with lower conductivity is provided between part of the first semiconductor layer and part of the first electrode. The first electrode has an electrode width. The electrode width is in a direction perpendicular to a direction in which the first electrode extends. The electrode width decreases with distance from the electrode pad.Type: GrantFiled: September 3, 2015Date of Patent: October 18, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Satoshi Mitsugi, Hiroshi Katsuno
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Patent number: 9466763Abstract: A semiconductor light-emitting element includes a substrate and a semiconductor stack portion provided on the substrate and having at least a first-conductivity-type semiconductor layer, a light-emitting layer, and a second-conductivity-type semiconductor layer. The substrate has a property to allow transmission of light from the light-emitting layer, and has a hexahedral shape including a first surface on which a semiconductor stack portion is provided, a second surface located opposite to the first surface, a pair of third surfaces orthogonal to the first surface and the second surface, and a pair of fourth surfaces orthogonal to the first surface and the second surface and different from the pair of third surfaces.Type: GrantFiled: June 10, 2014Date of Patent: October 11, 2016Assignee: Sharp Kabushiki KaishaInventors: Hiroaki Yamamoto, Susumu Ohmi, Yufeng Weng, Kiminori Tanabe
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Patent number: 9455300Abstract: Embodiments of the invention include a first semiconductor layer grown over a growth substrate and a plurality of pixels grown on the first semiconductor layer, each pixel including an active layer disposed between an n-type region and a p-type region. Trenches isolate individual pixels and form at least one sidewall for each pixel. A first metal layer in direct contact with the p-type region is disposed on a top surface of each pixel. A second metal layer in direct contact with the n-type region is disposed on a bottom surface of a trench adjacent to each pixel. An insulating layer electrically isolating the first and second metal layers is disposed on the sidewall of each pixel and is substantially conformal to the sidewall.Type: GrantFiled: March 19, 2015Date of Patent: September 27, 2016Assignee: RayVio CorporationInventors: Douglas A. Collins, Li Zhang, Faisal Sudradjat
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Patent number: 9425293Abstract: A threshold voltage tuning approach for forming a stacked nanowire gate-all around pFET is provided. In the present application, selective condensation (i.e., oxidation) is used to provide a threshold voltage shift in silicon germanium alloy nanowires. The threshold voltage shift is well controlled because both underlying parameters which govern the final germanium content, i.e., nanowire width and amount of condensation, are well controlled by the selective condensation process. The present application can address the problem of width quantization in stacked nanowire FETs by offering various device options.Type: GrantFiled: December 30, 2015Date of Patent: August 23, 2016Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9412922Abstract: A wafer level light-emitting diode (LED) array includes: a growth substrate; a plurality of LEDs arranged over the substrate, each including a first semiconductor layer, an activation layer, and a second semiconductor layer; a plurality of upper electrodes formed from a common material and electrically connected to the first semiconductor layers of the corresponding LEDs; and first and second pads arranged over the upper electrodes. The LEDs are connected in series by the upper electrodes, the first pad is electrically connected to an input LED from among the LEDs connected in series, and the second pad is electrically connected to an output LED from among the LEDs connected in series. Accordingly, a flip chip-type LED array can be provided which can be driven with a high voltage.Type: GrantFiled: August 6, 2013Date of Patent: August 9, 2016Assignee: SEOUL VIOSYS CO., LTD.Inventors: Jong Min Jang, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A. Kim, Won Young Roh, Min Woo Kang
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Patent number: 9406841Abstract: To improve efficiency when manufacturing a light emitting device formed using a mask to form regions corresponding to pixels on a substrate, provided is a method including, after forming a pattern on a substrate with a first light emitting material that emits light of a first spectrum, through a first opening and one or more second openings of a mask, moving the mask in a longitudinal direction of the first opening by a distance that is less than the width of the first opening in the longitudinal direction of the first opening and greater than or equal to the width of the one or more second openings in the longitudinal direction of the first opening, and then forming a pattern with a second light emitting material that emits light of a second spectrum, through the first opening and the one or more second openings of the mask.Type: GrantFiled: September 5, 2014Date of Patent: August 2, 2016Assignee: KANEKA CORPORATIONInventors: Hideo Yamagishi, Akimine Hayashi
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Patent number: 9379096Abstract: A semiconductor device includes a plurality of semiconductor elements; first semiconductor chips including first semiconductor elements, the first semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements and having a current flowing greater than that of the other semiconductor elements; second semiconductor chips having second semiconductor elements, the second semiconductor elements being defined as semiconductor elements in the plurality of semiconductor elements for controlling the first semiconductor elements; an insulating substrate having a first wiring pattern bonded with the first semiconductor chips; and an insulating member having a second wiring pattern mounted with the second semiconductor chips.Type: GrantFiled: September 11, 2014Date of Patent: June 28, 2016Assignee: FUJI ELECTRIC CO., LTD.Inventors: Toshio Denta, Tomonori Seki, Tadanori Yamada, Tadahiko Sato
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Patent number: 9373754Abstract: A laminate capable of emitting light comprises a reflective layer. The reflective layer increases the amount of light output from the laminate. A lighting apparatus containing the improved laminate is also provided.Type: GrantFiled: July 30, 2014Date of Patent: June 21, 2016Assignee: NthDegree Technologies Worldwide IncInventors: Erik John Hasenoehrl, Kenneth Stephen McGuire
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Patent number: 9368707Abstract: To provide a mounting substrate wherein insulation resistance of a metal substrate having an oxide film formed on the surface thereof is ensured, and light reflectance is improved by preventing a light-reflecting material contained in a reflection layer from diffusing into a surface of the metal substrate. A mounting substrate includes a metal substrate (21), and a surface layer section (22) formed on an upper surface of the metal substrate (21). The surface layer section (22) includes an oxide film layer (23) formed on a surface of the metal substrate (21), a barrier layer (24) formed on the oxide film layer (23), a reflection layer (25) formed on the barrier layer (24) and containing a light-reflecting material, and a protection film layer (26) formed on the reflection layer (25).Type: GrantFiled: March 14, 2013Date of Patent: June 14, 2016Assignees: CITIZEN ELECTRONICS CO., LTD., CITIZEN HOLDINGS CO., LTD.Inventor: Sadato Imai
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Patent number: 9349995Abstract: A method is disclosed for making a hybrid solar cell comprising organic and inorganic materials on an inexpensive substrate, such as glass. The materials are deposited on the substrate at low temperatures using eutectics and crystalline buffer layers such as MgO and Al2O3. Such a device can also be used for OLETs and OLEDs used in displays.Type: GrantFiled: December 16, 2014Date of Patent: May 24, 2016Assignee: Solar-Tectic LLCInventor: Ashok Chaudhari
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Patent number: 9337238Abstract: Selector elements that can be suitable for nonvolatile memory device applications are disclosed. The selector element can have low leakage currents at low voltages to reduce sneak current paths for non-selected devices, and higher leakage currents at higher voltages to minimize voltage drops during device switching. The selector element can be based on multilayer film stacks (e.g. metal-semiconductor-metal (MSM) stacks). The semiconductor layer of the selector element can include a photo-luminescent or electro-luminescent material. Conductive materials of the MSM may include tungsten, titanium nitride, carbon, or combinations thereof.Type: GrantFiled: October 27, 2014Date of Patent: May 10, 2016Assignee: Intermolecular, Inc.Inventors: Kevin Kashefi, Ashish Bodke, Mark Clark, Prashant B. Phatak, Dipankar Pramanik
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Patent number: 9324913Abstract: A nitride semiconductor structure includes: a plurality of crystal growth seed regions formed of a nitride semiconductor, of which the principal surface is an m-plane and which extends to a range that defines an angle of not less than 0 degrees and not more than 10 degrees with respect to an a-axis; and a laterally grown region formed of a nitride semiconductor which has extended in a c-axis direction from each of the plurality of crystal growth seed regions. An S width that is the spacing between adjacent ones of the plurality of crystal growth seed regions is at least 20 ?m.Type: GrantFiled: June 2, 2014Date of Patent: April 26, 2016Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Songbaek Choe, Shunji Yoshida, Toshiya Yokogawa
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Patent number: 9318529Abstract: A light emitting diode array is provide to include: a substrate; light emitting diodes positioned over the substrate, each including a first semiconductor layer, an active layer, and a second semiconductor layer, wherein each light emitting diode is disposed to form a first via hole structure exposing a portion of the corresponding first semiconductor layer; lower electrodes disposed over the second semiconductor layer; a first interlayer insulating layer disposed over the lower electrodes and configured to expose the portion of the first semiconductor layer of corresponding light emitting diodes; upper electrodes electrically connected to the first semiconductor layer through the first via hole structure, wherein the first via hole structure is disposed in parallel with one side of the corresponding second semiconductor layer and the first interlayer insulating layer is disposed to form a second via hole structure exposing a portion of the lower electrodes.Type: GrantFiled: May 26, 2015Date of Patent: April 19, 2016Assignee: Seoul Viosys Co., Ltd.Inventors: Jong Min Jang, Jong Hyeon Chae, Joon Sup Lee, Daewoong Suh, Hyun A. Kim, Won Young Roh, Min Woo Kang
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Patent number: 9312438Abstract: An epitaxial structure of light emitting diode with a current modulation layer, and more specifically, a high-resistivity material is injected to change the current conduction path, and implementation of the main structure is to grow a high-resistivity material (e.g., InxAlyGa1-x-yN) over the N-type conductive layer or the P-type conductive layer till part of current conduction path is exposed through high-temperature H2 in-situ etching in the reacting furnace and to grow the N-type or the P-type conductive layer for coverage. This design for forming a current modulation layer without second epitaxial growth provides the injected current with a better spreading path in the N-type conductive layer and the P-type conductive layer, which more effectively and uniformly injects the current to the active layer and improves luminous efficiency.Type: GrantFiled: May 21, 2015Date of Patent: April 12, 2016Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Wen-Yu Lin, Meng-Hsin Yeh, Kechuang Lin
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Patent number: 9306138Abstract: A packaging structure of a vertical LED chip includes at least a support system, a glue cup that connects to periphery of the support system, a LED chip with light absorption substrate over the support system and packaging glue distributed in periphery of the LED chip, wherein the packaging structure also comprises a baffle that surrounds the outer side wall of the light absorption substrate. Adding of a baffle structure in the support system of the packaging structure can effectively prevent light from being absorbed by the light absorption substrate and reflect such light out of the packaging structure, thus increasing probability of light emitting and improving light intensity of the vertical LED chip.Type: GrantFiled: June 17, 2015Date of Patent: April 5, 2016Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.Inventors: Chih-Wei Chao, Yen-Chih Chiang