Abstract: The present disclosure relates generally to a method to break and assemble solar cells to make solar panel. The present disclosure provides a method to produce solar pieces from solar cell, as well as assemble them together. The present disclosure device is unique when compared with other known devices and solutions because the present disclosure provides a high speed method to break scribed cells into pieces. A method of forming a string of solar cells includes providing a scribe line on a solar cell and placing a first ribbon on the solar cell. The method then includes placing the solar cell on a supporter and then breaking the solar cell into a plurality of solar cell pieces. The method then has the step of placing a second ribbon on the solar cell pieces and soldering the first and second ribbons and the solar cell pieces and then assembling the solar cell pieces into a string of solar cells.

Abstract: A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

Abstract: A system for welding a tub of a railroad tank car includes a manipulator boom adapted to move with respect to the interior surface of the tank shell. A hybrid laser arc welding head mounted to the manipulator. A supplemental gas metal arc welding head includes dual wires of welding material and is mounted to the manipulator adjacent to the hybrid laser arc welding head. An inductive heating coil is mounted adjacent to the supplemental gas metal arc welding head. The hybrid laser arc welding head welds a seam of the railroad tank car shell with the supplemental gas metal arc welding head following to generally complete filling of a resulting weld joint with welding metal. The supplemental gas metal arc welding head is followed with the inductive heating coil to provide heat to normalize the resulting weld joint.

Abstract: A quantum well device and a method for manufacturing the same are disclosed. In an embodiment, a quantum well structure comprises a quantum well region overlying a substrate and a remote counter doping comprising dopants of conductivity opposite to the conductivity of the charge carriers of the quantum well region. The remote counter doping is incorporated in a vicinity of the quantum well region for exchange mobile carriers with the quantum well channel, reducing the off-state leakage current. In another embodiment, a quantum well device comprises a quantum well structure including a remote counter doping, a gate region overlying a portion of the quantum well structure, and a source and drain region adjacent to the gate region. The quantum well device can also comprise a remote delta doping comprising dopants of the same conductivity as the quantum well channel.

Abstract: The use of a monolayer or partial monolayer sequencing process, such as atomic layer deposition (ALD), to form a zirconium substituted layer of barium titanium oxide (BaTiO3), produces a reliable ferroelectric structure for use in a variety of electronic devices such as a dielectric in nonvolatile random access memories (NVRAM), tunable dielectrics for multi layer ceramic capacitors (MLCC), infrared sensors and electro-optic modulators. In various embodiments, structures can be formed by depositing alternating layers of barium titanate and barium zirconate by ALD on a substrate surface using precursor chemicals, and repeating to form a sequentially deposited interleaved structure of desired thickness and composition. Such a layer may be used as the gate insulator of a MOSFET, or as a capacitor dielectric.

Abstract: A conductive pillar for a semiconductor device is provided. The conductive pillar is formed such that a top surface is non-planar. In embodiments, the top surface may be concave, convex, or wave shaped. An optional capping layer may be formed over the conductive pillar to allow for a stronger inter-metallic compound (IMC) layer. The IMC layer is a layer formed between solder material and an underlying layer, such as the conductive pillar or the optional capping layer.

Abstract: A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.

Abstract: Isolated conductive nanoparticles on a dielectric layer and methods of fabricating such isolated conductive nanoparticles provide charge traps in electronic structures for use in a wide range of electronic devices and systems. In an embodiment, conductive nanoparticles are deposited on a dielectric layer by a plasma-assisted deposition process such that each conductive nanoparticle is isolated from the other conductive nanoparticles to configure the conductive nanoparticles as charge traps.

Abstract: Structures and methods of forming an ideal MIM capacitor are disclosed. The single capacitor includes a first and a second metal structure overlying a substrate, a first dielectric material disposed between a first portion of the first metal structure and a first portion of the second metal structure. A second dielectric material is disposed between a second portion of the first metal structure and a second portion of the second metal structure. No first dielectric material is disposed between the second portion of the first and second metal structures, and no second dielectric material is disposed between the first portion of the first and second metal structures. The first and second dielectric material layers include materials with opposite coefficient of capacitance.

Abstract: The present invention relates to a method for producing a vertical interconnect structure, a memory device and an associated production method, in which case, after the formation of a contact region in a carrier substrate a catalyst is produced on the contact region and a free-standing electrically conductive nanoelement is subsequently formed between the catalyst and the contact region and embedded in a dielectric layer.

Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract: A modular multi-turbine unit of fixed toroidal support structures having a rail system designed to allow each of the plurality of turbines to rotate to a most efficient position relative to the wind for generating power, a computer control system capable of positioning each of the plurality of turbines to most effectively generate power from the wind, preventing damage to the turbines, and providing a wind predictive model based on the wind characteristics for the area in which the wind turbine is located.

Abstract: The embodiment of the invention provides a manufacturing method for a thin film transistor liquid crystal display (TFT-LCD) array substrate, the manufacturing method comprises: step 1, depositing a transparent conductive film, a source/drain metal film and a doped semiconductor film on a transparent substrate sequentially, forming patterns of a doped semiconductor layer, a source electrode and a drain electrode of a thin film transistor, a data line and a pixel electrode by a first patterning process, wherein the doped semiconductor layer remains on the source electrode and the drain electrode; Step 2, depositing a semiconductor film on the whole transparent substrate after Step 1, forming a pattern of a semiconductor layer which includes a channel of the thin film transistor by a second patterning process; Step 3, depositing an insulating film and a gate metal film on the whole transparent substrate after Step 2, forming patterns of a gate line and a gate electrode of the thin film transistor by a third patt

Abstract: A blue light emitting compound is provided. The blue light emitting compound has a structure of the following Chemical Formula 1: wherein A1, A2, and A3 are each independently selected from the group consisting of hydrogen, a substituted or unsubstituted aromatic group, a hetero ring group, and an aliphatic group.

Abstract: Electronic apparatus and methods of forming the electronic apparatus include a silicon oxynitride layer on a semiconductor device for use in a variety of electronic systems. The silicon oxynitride layer may be structured to control strain in a silicon channel of the semiconductor device to modify carrier mobility in the silicon channel, where the silicon channel is configured to conduct current under appropriate operating conditions of the semiconductor device.

Abstract: A method and apparatus for an electronic substrate having a plurality of semiconductor devices is described. A thin film of nanowires is formed on a substrate. The thin film of nanowires is formed to have a sufficient density of nanowires to achieve an operational current level. A plurality of semiconductor regions are defined in the thin film of nanowires. Contacts are formed at the semiconductor device regions to thereby provide electrical connectivity to the plurality of semiconductor devices. Furthermore, various materials for fabricating nanowires, thin films including p-doped nanowires and n-doped nanowires, nanowire heterostructures, light emitting nanowire heterostructures, flow masks for positioning nanowires on substrates, nanowire spraying techniques for depositing nanowires, techniques for reducing or eliminating phonon scattering of electrons in nanowires, and techniques for reducing surface states in nanowires are described.

Abstract: In order to solve a problem of increased noise accompanying increased area of a return path in a stacked package structure, provided is a semiconductor device which is formed in a stacked package such as a PoP package, which realizes low noise without changing a package size. An additional power supply wiring that runs along a signal wiring between an upper PoP and a lower PoP is newly added in the lower PoP of a package having a PoP structure.

Abstract: Disclosed is an organic electroluminescence device containing a pair of electrodes on a substrate, two or more luminescence layers disposed between the electrodes, and an intermediate layer containing a charge transporting material and disposed between the two or more luminescence layers, each of the two or more luminescence layers contains at least one phosphorescence material selected from a blue phosphorescence material having an emission peak from 420 nm to less than 500 nm, a green phosphorescence material having an emission peak from 500 nm to less than 570 nm, and a red phosphorescence material having an emission peak from 570 nm to 650 nm, the phosphorescence material contained in the respective luminescence layers having different emission peaks from one another; and the charge transporting material contained in the intermediate layer has an energy difference (T1) of 2.

Abstract: A disclosed embodiment is a programmable integrated circuit such as an audio processor or a base band processor for generating a low noise and programmable microphone bias voltage or current. The programmable integrated circuit generates a programmable reference input, where the reference input is programmably generated from at least one power source, such as a on-chip audio power supply, an on-chip power supply, or an off-chip power supply, for use by a regulator. The regulator in the programmable integrated circuit receives a bias input and the programmable reference input and generates a programmable output for biasing a microphone. The bias input for the regulator can be provided by an off-chip power supply or an on-chip power supply. The reference input provided to the regulator can be appropriately filtered to reduce noise. In one embodiment, the programmable reference input and the programmable output are programmed by first and second potentiometers, respectively.

Abstract: A phase change memory device having an improved word line resistance and a fabrication method of making the same are presented. The phase change memory device includes a semiconductor substrate, a word line, an interlayer insulation film, a strapping line, a plurality of current paths, a switching element, and a phase change variable resistor. The word line is formed in a cell area of the semiconductor substrate. The interlayer insulation film formed on the word line. The strapping line is formed on the interlayer insulation film such that the strapping line overlaps on top of the word line. The current paths electrically connect together the word line with the strapping line. The switching element is electrically connected to the strapping line. The phase change variable resistor is electrically connected to the switching element.