Abstract: A semiconductor device and a method of manufacturing the same, to appropriately determine an impurity concentration distribution of a field relieving region and reduce an ON-resistance. The semiconductor device includes a substrate, a first drift layer, a second drift layer, a first well region, a second well region, a current control region, and a field relieving region. The first well region is disposed continuously from an end portion adjacent to the vicinity of outer peripheral portion of the second drift layer to a portion of the first drift layer below the vicinity of outer peripheral portion. The field relieving region is so disposed in the first drift layer as to be adjacent to the first well region.

Abstract: A solid-state image capturing device according to the present invention includes: a photoelectrical conversion section formed in a semiconductor substrate or in a substrate area provided on a substrate; a first transparent film provided on the photoelectrical conversion section; and a lens provided at a position above the first transparent film corresponding to the photoelectrical conversion section, where the lens is formed by using a second transparent film layered by changing a refractive index successively or incrementally, and at least one of top and bottom surfaces of the second transparent film is formed in a convex shape.

Abstract: An apparatus and a muting circuit. The apparatus comprises an amplifier, a mute circuit, a pull-down circuit, and a power detection circuit. The amplifier receives a power supply voltage and a common mode voltage, and amplifies an audio input signal to generate an audio output signal. The mute circuit, coupled to the amplifier, conducts the audio output signal to about ground level upon receiving a mute signal. The pull-down circuit, coupled to the amplifier, pulls the common mode voltage to about ground level upon receiving a pull-down signal. The power detection circuit, coupled to the mute circuit and the pull-down circuit, detects power-up or power-down of the power supply voltage, and generates the mute signal and a pull-down signal according to the power-up or power-down operation.

Abstract: A semiconductor chip includes a circuit region and a corner stress relief (CSR) region. The CSR region is in a corner of the semiconductor chip. A device under test (DUT) structure or a functional circuit is disposed on the circuit region. A probe pad is disposed on the CSR region. A metal line extends from the circuit region to the CSR region to electrically connect the probe pad to the DUT structure or a functional circuit.

Abstract: Methods and apparatus for producing a gallium nitride semiconductor on insulator structure include: bonding a single crystal silicon layer to a transparent substrate; and growing a single crystal gallium nitride layer on the single crystal silicon layer.

Abstract: According to an embodiment disclosed herein, a microelectronic device to be encapsulated is built on, or alternatively in, a substrate. The device is then coated with a sacrificial layer. A lid layer is deposited over the sacrificial layer, and then appropriately perforated to optimize the removal of the sacrificial layer. The sacrificial layer is then removed using one of several etching or other processes. The perforations in the lid layer are then sealed using a viscous sealing material, thereby fixing the environment that encapsulates the device. The sealing material is then cured or hardened. An optional moisture barrier may be deposited over the cured sealing layer to provide further protection for the encapsulation if needed.

Abstract: In an active-matrix substrate (100) according to the present invention, a semiconductor layer (110) has a first gettering region (112) adjacent to the source region (132) of a first thin-film transistor (130), a second gettering region (114) adjacent to the drain region (146) of a second thin-film transistor (140), and a third gettering region (116) adjacent to any of the source and drain regions located between the respective channel regions (134 and 144) of the first and second thin-film transistors (130 and 140) among the source and drain regions of the thin-film transistors included in the thin-film transistor element (120).

Abstract: A solid-state imaging device including an imaging region having a plurality of pixels arranged in a two-dimensional matrix and a peripheral circuit detecting output signals from the pixels. An impurity concentration in a transistor of each pixel is lower than an impurity concentration in a transistor of the peripheral circuit. Further, the impurity concentration of a semiconductor well region under a floating diffusion portion in the pixel is set to be lower than the impurity concentration of a semiconductor well region under a transistor portion at the subsequent stage of the floating diffusion portion.

Abstract: Acoustic reflective devices are provided. An acoustic reflective device is configured to be inserted into an orifice. The device includes a stressing device that can vary a volume in response to a voltage difference across a portion of the stressing device. The stressing device is at least partially surrounded by a membrane.

Abstract: A reliable semiconductor light-emitting device and a method for manufacturing the same can be provided in which peeling can be prevented in a phase boundary, and optical axis positional errors between the optical lens and a semiconductor light-emitting chip can be reduced or prevented. The semiconductor light-emitting device can include a base board having at least one chip, a reflector fixed on the base board so as to enclose the chip, and an encapsulating resin disposed in the reflector. An optical lens can include a concave-shaped cavity that has an inner corner surface having a plurality of convex portions thereon. The optical lens can be located adjacent the reflector by contacting the lens with a top surface of the reflector so as to enclose the reflector. A spacer that is disposed between the concave-shaped cavity and the reflector can ease a stress that is generated due to temperature changes.

Abstract: A method for fabricating an FET device is disclosed. The method includes Fin-FET devices with fins that are composed of a first material, and then merged together by epitaxial deposition of a second material. The fins are vertically recesses using a selective etch. A continuous silicide layer is formed over the increased surface areas of the first material and the second material, leading to smaller resistance. A stress liner overlaying the FET device is afterwards deposited. An FET device is also disclosed, which FET device includes a plurality of Fin-FET devices, the fins of which are composed of a first material. The FET device includes a second material, which is epitaxially merging the fins. The fins are vertically recessed relative to an upper surface of the second material. The FET device furthermore includes a continuous silicide layer formed over the fins and over the second material, and a stress liner covering the device.

Abstract: A semiconductor device includes a substrate wafer, a dielectric layer overlying the substrate wafer, a patterned conductor layer in the dielectric layer, and a first barrier layer overlying the conductor layer. A silicon top wafer is bonded to the dielectric layer. A via is formed through the top wafer and a portion of the dielectric layer to the first barrier layer. A sidewall dielectric layer is formed along inner walls of the via, adjacent the top wafer to a distance below an upper surface of the top wafer, forming a sidewall dielectric layer shoulder. A sidewall barrier layer is formed inward of the sidewall dielectric layer, lining the via from the first barrier layer to the upper surface of the top wafer. A conductive layer fills the via and a top barrier layer is formed on the conductive layer, the sidewall barrier layer, and the top wafer.

Abstract: A method for manufacturing an integrated circuit package system includes: forming a first device unit, having first external interconnects arranged along a perimeter of the first device unit, and a second device unit, having second external interconnects arranged along a perimeter of the second device unit, in an array configuration; mounting an integrated circuit die over the first device unit; connecting the integrated circuit die and the first external interconnects; encapsulating with an encapsulation covering the integrated circuit die, the first device unit, and the second device unit with both the first external interconnects and the second external interconnects partially exposed; and forming a partial encapsulation cut in the encapsulation electrically isolating the first external interconnects and the second electrical interconnects.

Abstract: The switching element of the present invention is of a configuration that includes: an ion conduction layer (40) that includes an oxide, a first electrode (21) and a second electrode (31) that are provided in contact with the ion conduction layer (40) and that are connected by the precipitate of metal that is supplied from the outside or for which electrical properties change due to the dissolution of precipitated metal, and a third electrode (35) provided in contact with the ion conduction layer (40) and that can supply metal ions. The use of this configuration allows the switching voltage to be set higher than in the related art.

Abstract: The present method includes: forming a device isolation region in a substrate dividing the device isolation region into first and second diffusion regions; forming a target film to be processed on the substrate; forming a hard mask layer and a first resist layer on the film; forming a first pattern on the first resist layer; etching the hard mask layer using the first pattern as a mask; forming a second resist layer on the hard mask layer; forming a second pattern including a first space on the second resist layer isolating the first pattern; forming a third pattern including a second space shrunk from the first space on the hard mask layer by carrying out size conversion etching by using the second pattern formed on the second resist layer as a mask; and etching the film to be processed by using the third pattern formed on the hard mask layer.

Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.

Abstract: Methods for fabricating a semiconductor memory cell that has a spacer layer are disclosed. A method includes forming a plurality of source/drain regions in a substrate where the plurality of source/drain regions are formed between trenches, forming a first oxide layer above the plurality of source/drain regions and in the trenches, forming a charge storage layer above the oxide layer and separating the charge storage layer in the trenches where a space is formed between separated portions of the charge storage layer. The method further includes forming a spacer layer to fill the space between the separated portions of the charge storage layer and to rise a predetermined distance above the space. A second oxide layer is formed above the charge storage layer and the spacer layer and a polysilicon layer is formed above the second oxide layer.

Abstract: Provided are electronic device packages and their methods of formation. The electronic device packages include an electronic device mounted on a substrate, a conductive via and a locally thinned region in the substrate. The invention finds application, for example, in the electronics industry for hermetic packages containing an electronic device such as an IC, optoelectronic or MEMS device.

Abstract: A method of forming a through silicon via (TSV) structure includes forming an interconnect pad over a substrate. An under layer is formed over the interconnect pad. A vertical conductive post is formed at least partially through the substrate. At least one dummy structure is formed at least partially through the under layer. A top pad is formed over the dummy structure and the vertical conductive post. The top pad covers a wider area than a cross section of the vertical conductive post. The interconnect pad is electrically connected to the top pad. The dummy structure connects the top pad and the under layer thereby fastening the top pad and the interconnect pad.

Abstract: An integrated circuit comprising both memory and logic wherein at least one layer of the integrated circuit is fabricated using a common grating pattern for both memory and logic is described. In one embodiment, the integrated circuit comprises a substrate, an active layer, and a gate material layer such as a polysilicon layer, and the active layer, the gate material layer, or both the active layer and the gate material layer are formed using a common grating pattern for both memory and logic. By using a common grating pattern for both memory and logic, a corresponding layer of the integrated circuit can be reliably and affordably manufactured using sub-wavelength lithography.