Abstract: A semiconductor integrated circuit includes a first cell spanning one of the p-wells and one of the n-wells adjacent to each other, and having one end on a dividing line inside the p-well and another end on a dividing line inside the n-well, and having a height determined by the one end and the another end; and a second cell, spanning another one of the p-wells and another one of the n-wells adjacent to each other, with a height covering the entire widths of the p- and n-wells measured along the column direction, the height of the second cell is double that of the first cell.

Abstract: A method for forming a silicon-containing film is described. A substrate is placed in a reaction chamber, and then a silicon-containing gas is introduced into the reaction chamber to conduct a CVD process and deposit a silicon-containing film on the substrate. During the CVD process, the temperature of at least the top inner surface of the reaction chamber is controlled below 50° C.

Abstract: A planar image detector with a number of photosensor elements arranged like a matrix, the photosensor elements being activated by at least one associated switching element and respectively exhibiting at least one memory element with a predetermined capacity. A predetermined number of phototransistors each have a gate electrode that exhibits at least one gap in a gate metallization thereof and arranged between the source electrode and the drain electrode. The gap produces a space that is reduced in terms of field strength that can be realized simply in terms of production of such planar image detector.

Abstract: A method and apparatus for forming an electrically and/or thermally conducting interconnection is disclosed wherein a first surface and a second surface are contacted with each other via a plurality of nanostructures disposed on at least one of the surfaces. In one embodiment, a first plurality of areas of nanostructures is disposed on a component in an electronics package such as, illustratively, a microprocessor. The first plurality of areas is then brought into contact with a corresponding second plurality of areas of nanostructures on a substrate, thus creating a strong friction bond. In another illustrative embodiment, a plurality of nanostructures is disposed on a component, such as a microprocessor, which is then brought into contact with a substrate. Intermolecular forces result in an attraction between the molecules of the nanostructures and the molecules of the substrate, thus creating a bond between the nanostructures and the substrate.

Abstract: A method of producing an element separation structure includes the steps of: forming a first thermal oxide film on the substrate; forming a silicon nitride film on the first thermal oxide film; removing the first thermal oxide film and the silicon nitride film in an element separation structure forming region; forming a groove portion in the element separation structure forming region; forming a groove portion oxide film in the groove portion; forming a pre-filling oxide film for filling the groove portion; removing the pre-filling oxide film; forming a resist layer on the silicon nitride film and the pre-filling oxide film; forming a resist mask on the element separation structure forming region; removing the silicon nitride film and the first thermal oxide film; forming a second thermal oxide film on the substrate; and removing the second thermal oxide film and leveling the pre-filling oxide film to form a filling portion.

Abstract: The invention relates to a method for manufacturing at least one phase change memory cell. The method at least fabricating at least one first lamellar spacer of conductive material, which is electrically coupled to the PCM material of the memory cell; fabricating at least one second lamellar spacer on top of the first lamellar spacer, wherein the second lamellar spacer crosses the first lamellar spacer in the area of the PCM material; partially removing the first lamellar spacer, wherein the second lamellar spacer serves as a hardmask for partially removing the first lamellar spacer, so that the first lamellar spacer forms at least one electrode contacting an area of PCM material.

Abstract: A wiring line to which a high-frequency signal is applied is electrically connected in parallel to an auxiliary, wiring line via a plurality of contact holes. The contact holes are formed through an interlayer insulating film and arranged in vertical direction to the wiring line. Since the auxiliary wiring line is formed in the same layer as an electrode that constitutes a TFT, the electric resistance of the wiring line can be reduced effectively and waveform rounding of an applied high-frequency signal can be reduced without increasing the number of manufacturing steps.

Abstract: A dual damascene interconnect structure is formed by patterning a first dielectric to form a metal line. A second dielectric is disposed on the first dielectric and patterned to form a via. The first metal line is patterned in a configuration relative to a via landing so that a cavity is formed when the via etch into the second dielectric is extended into the first dielectric. The cavity is filled with a conductive metal in an integral manner with the formation of the via to form a via projection for improved electrical contact between the via and the metal line.

Abstract: In an organic photodiode, in a gap between a transparent anode formed on a glass substrate, and a reflection cathode formed oppositely thereto, a plurality of light receiving parts as layers of light absorbing composition, and partition walls for insulating between transparent anode and reflection cathode and insulating between adjacent light receiving parts are formed. Partition walls are formed by applying an ink solution to transparent anode and an insulating layer covering its periphery, dissolving the insulating layer by an organic solvent contained in the ink solution, and forming a plurality of dissolved holes contacting with transparent anode. The plurality of light receiving parts are formed by filling the plurality of dissolved holes with the light absorbing composition contained in the ink solution.

Abstract: Memory elements including a first electrode and a second electrode. A chalcogenide material layer is between the first and second electrodes and a tin-chalcogenide layer is between the chalcogenide material layer and the second electrode. A selenide layer is between the tin-chalcogenide layer and the chalcogenide material layer. Optionally, a metal layer, for example a silver layer, is between the tin-chalcogenide layer and the second electrode. Methods for forming the memory elements are also provided.

Abstract: A semiconductor device comprises: a semiconductor chip; an extension portion which contacts the side surfaces of the semiconductor chip to thereby surround the semiconductor chip; an insulating film which is formed such that a part of each of the plurality of electrode pads is exposed; a plurality of wiring patterns individually electrically connected to each of the electrode pads, respectively and extended from the electrode pads to the upper side of the extension portion; and a plurality of external terminals provided over the wiring patterns in a region including the upper side of the extension portion.

Abstract: Doped aluminum oxide layers having a porous aluminum oxide layer and methods of their fabrication. The porous aluminum oxide layer may be formed by evaporation physical vapor deposition techniques to facilitate formation of a high-purity aluminum oxide layer. A dopant material is embedded in the pores of the porous aluminum oxide layer and subsequently converted to a dielectric form. The degree of porosity of the porous aluminum oxide layer may be controlled during formation to facilitate control of the level of doping of the doped aluminum oxide layer. Such doped aluminum oxide layers are useful as gate dielectric layers, intergate dielectric layers and capacitor dielectric layers in various integrated circuit devices.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: A pin diode is formed by a p+ collector region, an n type buffer region, an n? region and an n+ cathode region. A trench is formed from the surface of n+ cathode region through n+ cathode region to reach n? region. An insulating film is formed along an inner wall surface of trench. A gate electrode layer is formed to oppose to the sidewall of n+ cathode region with insulating film interposed. A cathode electrode is formed to be electrically connected to n+ cathode region. An anode electrode is formed to be electrically connected to p+ collector region. The n+ cathode region is formed entirely over the surface between trenches extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Abstract: A semiconductor assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: Methods of forming thin film transistors, and transistors therefrom, are provided where at least one of the source or drain region is conductively doped while conductivity doping of the channel region is prevented without any masking by any separate masking layer. Methods include, providing a substrate having a conductive node; providing a first dielectric layer, a gate layer over the first layer and a second dielectric layer over the gate layer; providing a contact opening through the first and second layers and the gate layer, the opening defining projecting sidewalls; providing a gate dielectric layer within the opening; providing a layer of semiconductive material over the second layer, against the gate dielectric layer and in electrical communication with the node; the material defining a channel region; and conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region.