Thin film transistor

Methods of forming thin film transistors, and transistors therefrom, are provided where at least one of the source or drain region is conductively doped while conductivity doping of the channel region is prevented without any masking by any separate masking layer. Methods include, providing a substrate having a conductive node; providing a first dielectric layer, a gate layer over the first layer and a second dielectric layer over the gate layer; providing a contact opening through the first and second layers and the gate layer, the opening defining projecting sidewalls; providing a gate dielectric layer within the opening; providing a layer of semiconductive material over the second layer, against the gate dielectric layer and in electrical communication with the node; the material defining a channel region; and conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region.

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Description
RELATED PATENT DATA

This patent application is a divisional application of U.S. patent application Ser. No. 08/996,325 which was filed Dec. 22, 1997, now U.S. Pat. No. 6,589,821 which issued Jul. 8, 2003, which is a continuation application of U.S. patent application Ser. No. 08/506,084, filed Jul. 24, 1995, now U.S. Pat. No. 5,700,727 which issued Dec. 23, 1997, the disclosures of which are incorporated herein by reference.

PATENT RIGHTS STATEMENT

This invention was made with Government support under Contract No. MDA972-92-C-0054 awarded by Advanced Research Projects Agency (ARPA). The Government has certain rights in this invention.

TECHNICAL FIELD

This invention relates specifically to thin film transistor technology.

BACKGROUND OF THE INVENTION

As circuit density continues to increase, there is a corresponding drive to produce smaller and smaller field effect transistors. Field effect transistors have typically been formed by providing active areas is within a bulk substrate material or within a complementary conductivity type well formed within a bulk substrate. One additional technique finding greater application in achieving reduced transistor size is to form field effect transistors with thin films, which is commonly referred to as “thin film transistor” (TFT) technology. These transistors are formed using thin layers which constitute all or a part of the resultant source and drain regions, as opposed to providing both regions within a bulk semiconductor substrate.

Specifically, typical prior art TFT's are formed from a thin film of semiconductive material (typically polysilicon). A central channel region of the thin film is masked by a separate layer, while opposing adjacent source/drain regions are doped with an appropriate p or n type conductivity enhancing impurity. A gate insulator and gate are provided either above or below the thin film channel region, thus providing a field effect transistor having active and channel regions formed within a thin film as opposed to a bulk substrate.

It would be desirable to improve upon methods of forming thin film transistors and in improving thin film transistor constructions.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.

FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.

FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 2.

FIG. 4 is one example of a possible top view of FIG. 3.

FIG. 5 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 3.

FIG. 6 is a diagrammatic sectional view of an alternate embodiment wafer fragment in accordance with the invention.

FIG. 7 is a diagrammatic sectional view of yet another alternate embodiment wafer fragment at one processing step in accordance with the invention.

FIG. 8 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 7.

FIG. 9 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 8.

FIG. 10 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 9.

FIG. 11 is a view of the FIG. 7 wafer fragment at a processing step subsequent to that shown by FIG. 10.

 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section-8).

In accordance with one aspect of the invention, a method of forming a thin film transistor over a substrate comprises the following steps:

providing a layer of semiconductive material from which a channel region and at least one of a source region or a drain region of a thin film transistor are to be formed; and

conductively doping the at least one of the source region or the drain region of the semiconductive material layer while preventing conductivity doping of the channel region of the semiconductive material layer, such doping being conducted without any masking of the channel region by any separate masking layer.

In accordance with another aspect of the invention, a method of forming a thin film transistor comprises the following steps:

providing a substrate having a node to which electrical connection is to be made;

providing a first electrically insulative dielectric layer over the substrate;

providing an electrically conductive gate layer over the first dielectric layer;

providing a second electrically insulative dielectric layer over the electrically conductive gate layer;

providing a contact opening through the second dielectric layer, the electrically conductive gate layer and the first dielectric layer; the is contact opening defining projecting sidewalls;

providing a gate dielectric layer within the contact opening laterally inward of the contact opening sidewalls;

providing a layer of semiconductive material over the second dielectric layer and within the contact opening against the gate dielectric layer and in electrical communication with the node; the semiconductive material within the contact opening defining an elongated and outwardly extending channel region the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers; and

conductively doping the semiconductive material layer lying outwardly of the contact opening to form one of a source region or a drain region of a thin film transistor.

In accordance with still another aspect of the invention, a thin film transistor comprises:

a thin film transistor layer having a source region, a channel region and a drain region; the thin film channel region comprising an annulus; and

a gate in proximity to the thin film channel annulus, the gate comprising an annulus which surrounds the thin film channel annulus.

These and other aspects of the invention will be more readily appreciated from the following description which proceeds with reference to the accompanying drawings.

Referring to FIG. 1, a semiconductor wafer fragment in process is indicated generally with reference numeral 10. Such comprises a bulk substrate 12 of lightly doped p or n type monocrystalline silicon, having a diffusion region 13 provided therein. A first electrically insulative dielectric layer 14 (typical SiO2) is provided over bulk substrate 12. An example and preferred thickness range for layer 12 is from 50 Angstroms to 2000 Angstroms, with 100 Angstroms being more preferred. An electrically conductive layer 16 is provided over first dielectric layer 14. Layer 16 will ultimately comprise the conductive gate of the thin film transistor, and preferably comprises a heavily doped (greater than 1×1020 ion/cm3) layer of polysilicon. An example and preferred thickness range is from 3000 Angstroms to 10,000 Angstroms, with 8000 Angstroms being more preferred. A second electrically insulative dielectric layer 18 is provided over electrically conductive gate layer 16. Such can be considered as a base layer over which a thin film transistor layer will be provided. An example and preferred material is SiO2 deposited to a thickness range of from 300 Angstroms to 3000 Angstroms, with 1000 Angstroms being more preferred.

Referring to FIG. 2, a contact opening 20 is provided through second dielectric layer 18, electrically conductive gate layer 16, and first dielectric layer 14 to outwardly expose diffusion region 13. Alternately, diffusion region 13 could be provided after forming contact opening 20. One method of doing this is by using ion implantation through contact opening 20, thereby making diffusion regions 13 self-aligned to contact opening 20. Contact opening 20 defines projecting sidewalls 22 which in the preferred embodiment are provided to be substantially perpendicular relative to the expanse of bulk substrate 12. A dielectric layer 24, which will serve as gate dielectric layer, is deposited over second dielectric layer 18 and within contact opening 20 to a thickness which less than completely fills contact opening 20. An example diameter for contact opening 20 is 3500 Angstroms, with an example layer 24 being SiO2 deposited to a thickness of 200 Angstroms in such instance.

Referring to FIG. 3, gate dielectric layer 24 is anisotropically etched to define a resultant gate dielectric layer 26 within contact opening 20 laterally inward of sidewalls 22. When anisotropically etching gate dielectric layer 24, some of second dielectric layer 18 is removed during a desired overetch. If layer 18 is 1000 Angstroms thick and layer 24 is 200 Angstroms thick, a preferred over-etch would be 200 Angstroms, reducing 18 to 800 Angstroms. In the illustrated and preferred embodiment, such gate dielectric layer takes on the shape or appearance of conventional insulative sidewall spacers, and in the depicted embodiment is in the form or shape of a longitudinally elongated annulus. Thus, electrically conductive gate layer 16 also is comprised of an annulus which surrounds contact opening 20.

FIG. 4 illustrates one example of a possible patterned top construction of FIG. 3. Such illustrates gate dielectric annulus 26 encircling within contact opening 20. Electrically conductive gate layer 16 has been patterned to comprise a ring portion and an extension 27. Regardless, the bulk mass of layer 16 constitutes an annulus which encircles contact opening 20. The above described process provides but one example of a manner in which a gate dielectric layer is provided within contact opening 20.

Referring to FIG. 5, a layer 30 of semiconductive material is provided over second dielectric layer 18 and within contact opening 20 against gate dielectric layer 26, and in electrical communication with diffusion region 13. In this particular described embodiment, layer 30 is provided to completely fill the remaining open portion of contact opening 20. Semiconductive material layer 30 constitutes a layer from which a channel region and at least one of a source region or a drain region of a thin film transistor are to be formed. The semiconductive material of layer 30 within contact opening 20 defines an elongated and outwardly extending channel region 31 the electrical conductance of which can be modulated by means of the adjacent electrically conductive gate and gate dielectric layers 16 and 26, respectively.

Field effect transistor channel regions typically utilize some minimum conductivity doping, less than the doping concentrations of the source and drain, to provide desired conductance when modulated by the gate. Such can be provided in this example by in situ doping of layer 30 during its deposition. Alternately, an ion implant can be conducted with subsequent processing providing desired diffusion of the dopants.

The semiconductive material layer 30 is then conductively doped such that its portion lying outwardly of contact opening 20 forms one of a source or a drain region 32 of a thin film transistor. The doping results in an interface 34 being created relative to the outermost portions of layer 30 and that portion within channel region 31, such that portion 32 constitutes a highly doped electrically conductive region, while channel region 31 constitutes a semiconductive layer capable of being rendered conductive by applying suitable voltage to gate layer 16. Note that advantageously in accordance with the preferred process, conductive doping of layer 30 is conducted using its thickness to effectively prevent conductivity doping of channel region 31, with such doping being conducted without other masking of the channel region by any separate masking layer. The effective thickness and doping conditions for the outer portion of layer 30 effectively can be utilized to prevent undesired conductivity enhancing doping of channel region 31.

In the above described embodiment; one of doped regions 32 of layer 30 or diffusion region 13 of bulk substrate 12 constitutes a source region of a thin film transistor, while the other of such constitutes a drain region. Region 31 constitutes a channel region, with gate layer 16 comprising an annulus which encircles thin film channel region 31. Both of channel region 31 and diffusion region 32 are elongated, with diffusion region 32 being oriented substantially perpendicular relative to channel region 31 and also substantially parallel with bulk substrate 14. Elongated channel region 31 and gate dielectric annulus 26 are perpendicularly oriented relative to bulk substrate 14.

If region 13 constitutes the drain region, then the thickness of oxide layer 14 defines the gate-drain offset dimension of the thin film transistor. As well known to those of skill in the art, a drain offset is a region used in thin film transistors to reduce off current caused by thermionic field emission in the channel region near the drain. If region 32 is the drain, then the thickness of layer 18 defines the offset dimension. The thickness of gate polysilicon layer 16 defines the channel length of the thin film transistor.

An alternate embodiment is shown and described with reference to FIG. 6. Like numerals from the first described embodiment are utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. In the depicted embodiment of wafer fragment 10a, semiconductive material 30a is provided to only partially fill the remaining portion of contact opening 20. Such forms an annulus 33 within contact opening 20, with such annulus being utilized to comprise the channel region of the resultant thin film transistor.

Layer 30a can be doped in a single step to form diffusion regions 32a and 35, one of which constitutes a drain region and the other of which constitutes a source region of the resultant thin film transistor. Accordingly, channel annulus 33 is elongated and oriented substantially perpendicularly relative to bulk substrate 12 and diffusion regions 32a and 35. In this described embodiment, gate layer 16 comprises an annulus which surrounds thin film channel annulus 33. Again, the elongated and substantially vertical nature or orientation of channel region 33 prevents conductivity doping from occurring therein when regions 32a and 35 are doped by a highly directional perpendicular ion implantation doping. In this embodiment, diffusion region 13 constitutes a node to which electrical connection of a thin film transistor is to be made, while in the first embodiment example region 13 comprised an inherent part of the thin film transistor. Diffusion region 13 might alternately be provided by out-diffusion of dopant material from region 35 from subsequent heating steps.

Desired minimum doping for the channel region of FIG. 6 can be provided by in situ doping or by ion implanting, such as angled implanting.

Yet another alternate preferred embodiment is described with reference to FIGS. 7-11. Like numerals from the first described embodiment have been utilized where appropriate, with differences being indicated with the suffix “b” or with different numerals. Referring first to FIG. 7, second electrically insulative dielectric layer 18 is provided with an initial contact opening 50 therethrough to electrically conductive gate layer 16. A preliminary electrically insulative layer 52 is provided over second dielectric layer 18 and to within initial contact opening 50, with such layer less than completely filling contact opening 50.

Referring to FIG. 8, preliminary electrically insulative layer 52 is anisotropically etched to define an insulative annulus spacer 54 within initial contact opening 50. Such facilitates or enables producing a contact opening inwardly of the spacers which is less than the minimum photolithographic feature size which can be useable to produce the smallest possible initial contact opening 50. For example, where a minimum available photolithographic width for contact opening 50 were 0.32 micron, the resultant width of the opening after spacer etch can be reduced to 0.1 micron. As examples, if layer 18 is 1500 Angstroms thick and opening 50 is 3200 Angstroms in diameter, layer 52 is preferably provided to a thickness of from 500 Angstroms to 1200 Angstroms, with 1000 Angstroms being most preferred. An anisotropic etch of a 1000 Angstrom thick layer 52 will preferably be conducted as an over-etch of 300 Angstroms, leaving layer 18 1200 Angstroms thick.

Referring to FIG. 9, a secondary contact 56 is etched through electrically conductive gate layer 16 and first dielectric layer 14. During such etching, insulative annulus spacer 54 and second dielectric layer 18 are used as an etching mask. Diffusion regions 13b is provided as shown.

Referring to FIG. 10, a secondary electrically insulative layer 58 is provided over second dielectric layer 18 and insulative annulus spacer 54 to within secondary contact opening 56, with such layer being provided to less than completely fill secondary contact opening 56.

Referring to FIG. 11, secondary electrically insulative layer 58 has been anisotropically etched to define a gate dielectric layer annulus 26b within secondary contact opening 56. A subsequent semiconductive layer 30b is provided and doped as shown to provide diffusion region 32b, and to provide channel region 31b. An example thickness for layer 58 is 200 Angstroms. Anisotropic etching of such a layer preferably includes a 200 Angstrom over-etch, resulting in a final preferred thickness of layer 18 of 1000 Angstroms.

The above described embodiments utilizing an annulus gate essentially enables provision of a channel region which is gated about all sides, thus enabling provision of smaller field effect transistors. Such results in a reduced consumption of substrate area, with such example thin film transistors enabling the required area to be that of the contact and the associated anisotropic spacer-like constructions. Conventional horizontal thin film transistors require additional area for the channel, source and drain regions. Such also provides for improved thin film transistor characteristics, due to gating of the channel region on all sides which provides greater controllable on/off currents.

The above described method and embodiment further reduce overall mask count in semiconductor processing. Since in the preferred embodiment the channel region is substantially vertical, masks are not required to protect the desired channel from the thin film transistor source and drain implants. Depending on implementation, the channel region may even be completely sealed from the surface providing even greater protection, thus eliminating at least two masks.

In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A thin film transistor comprising:

a variable thickness thin film transistor layer, the transistor layer having a channel region elongated in an upward direction and one of a source region or a drain region elevationally above the channel region, the one region comprising a structure elongated in a lateral direction substantially perpendicular to the elongated upward direction of the channel region, and the one region having a dimension in the lateral direction greater than a greatest dimension of the channel region in the lateral direction; and
a gate in lateral proximity to the channel region, the gate comprising an annulus which laterally encircles the laterally proximate channel region.

2. The thin film transistor of claim 1, further comprising a substrate supporting the thin film transistor layer, and wherein the one region comprises the elongated structure oriented substantially parallel to the substrate.

3. The thin film transistor of claim 1, wherein the source region and the drain region are oriented parallel relative to one another, the channel region is oriented substantially perpendicularly relative to both the source and drain regions.

4. The thin film transistor of claim 1, wherein he source region and the drain region are provided in different elevational planes, the channel region is disposed elevationally between the source region and drain region.

5. The thin film transistor of claim 4, wherein the source region and the drain region having different thicknesses.

6. The thin film transistor of claim 1, wherein the channel region comprising an annulus encircled by the gate.

7. The thin film transistor of claim 1, further comprising:

a first dielectric layer disposed over a semiconductor substrate;
a gate electrode layer disposed over the first dielectric layer;
a second dielectric layer disposed over the gate electrode layer and having an upper surface; and
an opening extending through the second dielectric layer, the gate electrode layer and the first dielectric layer, the opening having opposing sidewalls and a bottom disposed between the opposing sidewalls.

8. The thin film transistor of claim 7, wherein the variable thickness thin film layer is disposed within the opening and extending outward from the opening and overlying at least a portion of the upper surface.

9. The thin film transistor of claim 7, wherein at least some of the one region is disposed over the upper surface of the second dielectric layer.

10. The thin film transistor of claim 7, further comprising a gate dielectric layer within the opening, at least a portion of the gate dielectric layer is elevationally coincident gate electrode layer.

11. A thin film transistor comprising:

a variable thickness thin film transistor layer supported over a substrate, the transistor layer having a thin film channel region, a first thin film source/drain (S/D) region and a second thin film S/D region, the first S/D region extending laterally in an elongated direction substantially parallel to surface of the substrate and having an elongated dimension greater than a greatest dimension of the second S/D region structure in a direction parallel to the surface of the substrate; and
a gate in lateral proximity to the thin film channel region, the gate comprising an annulus which laterally encircles the laterally proximate thin film channel region.

12. The thin film transistor of claim 11, wherein the first thin film S/D region is disposed elevationally above the thin film channel region.

13. The thin film transistor of claim 12, wherein the thin film channel region comprises an elongated structure oriented substantially perpendicularly relative to the elongated structure of the first thin film S/D region.

14. The thin film transistor of claim 11, wherein the first thin film S/D region and the second thin film S/D region are oriented parallel relative to one another, and wherein the thin film channel region is oriented substantially perpendicularly relative to both the first and second thin film S/D regions.

15. The thin film transistor of claim 11, wherein the first thin film S/D region and the second thin film S/D region are provided in different elevational planes, the channel region is disposed elevationally between the first and second thin film S/D regions.

16. The thin film transistor of claim 11, wherein the first thin film S/D region is provided elevationally above the second thin film S/D region.

17. The thin film transistor of claim 11, further comprising:

a first dielectric layer disposed over a semiconductor substrate;
a gate layer disposed over the first dielectric layer;
a second dielectric layer disposed over the gate layer and having an upper surface; and
an opening extending through the second dielectric layer, the gate layer and the first dielectric layer, the opening having opposing sidewalls and a bottom disposed between the opposing sidewalls, the thin film transistor is disposed within the opening and over the upper surface.

18. The thin film transistor of claim 17, wherein the first thin film S/D region is provided having at least a portion overlying the upper surface and the second thin film S/D region, and wherein the second thin film S/D region is provided having at least a portion overlying the bottom of the opening.

19. The thin film transistor of claim 17, further comprising a gate dielectric layer disposed within the opening adjacent the opposing sidewalls, where the thin film transistor layer is disposed over the gate dielectric layer.

20. The thin film transistor of claim 19, wherein the gate dielectric layer is an annulus received in the opening, the annulus having a top disposed elevationally below the upper surface.

21. A thin film transistor comprising:

a first dielectric layer disposed over a semiconductor substrate;
a gate electrode layer disposed over the first dielectric layer;
a second dielectric layer disposed over the gate electrode layer and having an upper surface, wherein the gate electrode layer and the second dielectric layer comprise an opening extending from the upper surface to the semiconductor substrate, the opening defining opposing sidewalls in the gate electrode layer;
a gate dielectric layer disposed over a portion of the sidewalls as an annulus, the annulus having a top that does not extend elevationally above the upper surface;
a channel region disposed within the opening, operably adjacent the gate dielectric layer; and
wherein the channel region completely fills the opening.

22. The thin film transistor of claim 21, further comprising one of a first diffusion region and a second diffusion region disposed over the upper surface and the channel region.

23. The thin film transistor of claim 21, further comprising one of a first diffusion region and a second diffusion region disposed over the upper surface and the channel region and the other of the first diffusion region and the second diffusion region disposed elevationally below the channel region.

24. The thin film transistor of claim 21, wherein the top of the annulus is below the upper surface.

25. The thin film transistor of claim 1 wherein the gate comprising the annulus comprises an opening through the gate.

26. The thin film transistor of claim 1 further comprising a bulk substrate configured to support the one region, and wherein an other of the source or drain regions is formed using the bulk substrate.

27. The thin film transistor of claim 11 wherein the gate comprising the annulus comprises an opening through the gate.

28. The thin film transistor of claim 11 further comprising the substrate wherein the first S/D region is formed over the substrate and the second S/D region is formed using the substrate.

29. The thin film transistor of claim 21 wherein the opening extends through an entirety of the gate electrode layer.

30. The thin film transistor of claim 21 further comprising:

the semiconductor substrate;
a first S/D region formed over the semiconductor substrate; and
a second S/D region formed in the semiconductor substrate.
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Patent History
Patent number: 6844577
Type: Grant
Filed: Aug 1, 2001
Date of Patent: Jan 18, 2005
Patent Publication Number: 20020048875
Assignee: Micron Technology, Inc. (Boise, ID)
Inventor: Monte Manning (Boise, ID)
Primary Examiner: Amir Zarabian
Assistant Examiner: Kiesha L. Rose
Attorney: Wells St. John P.S.
Application Number: 09/920,979