Patents Examined by Kim Huynh
  • Patent number: 10884467
    Abstract: Techniques relating to communicating system events in universal serial bus (USB) power delivery (PD) devices are described. In an example, a USB PD controller receives a notification of a system event in a first device associated with the USB PD controller, the system event being based on one of a change in machine state of the first device and occurrence of a user interaction event in the first device. A PD protocol based message, indicative of the system event in the first device, is generated. The PD protocol based message provides for activation of a predefined profile setting in a second device, wherein the second device is to interface with the first device through the USB PD controller.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 5, 2021
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Hua Shao, Chun-Qin Zhou, Xiao-Dong Zhang
  • Patent number: 10884472
    Abstract: A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.
    Type: Grant
    Filed: April 27, 2018
    Date of Patent: January 5, 2021
    Assignee: Oracle International Corporation
    Inventors: Yufei Qian, Yifan YangGong, Sebastian Turullols
  • Patent number: 10884468
    Abstract: A method, apparatus and computer program are provided for allocating power amount a plurality of computing devices. The method includes determining a current power capping amount for each of a plurality of computing devices and obtaining a current power usage of each computing device. The method further includes determining, for each computing device, an updated power capping amount based on whether or not the current power usage of the computing device has reached the current power capping amount of the computing device during a current period of time. The updated power capping amount is allocated to the respective computing devices, and a power supply is caused to deliver power to each computing device in an amount up to the updated power capping amount that has been allocated to the respective computing device.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: January 5, 2021
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Da Li, Shunrong Hu, Sheng Yan Xing
  • Patent number: 10880085
    Abstract: A method for creating devices facilitating secure data transmission, storage and key management. At least two devices are each comprised of at least part of a physically unclonable function unit originally shared by the at least two devices on a single, monolithic original integrated circuit. The process includes physically segmenting the shared physically unclonable function unit between the at least two devices. The at least two devices which share the single, monolithic integrated circuit are physically separated into individual device units.
    Type: Grant
    Filed: August 2, 2018
    Date of Patent: December 29, 2020
    Assignee: The University of Tulsa
    Inventors: Andrew Kongs, Gavin Bauer, Kyle Cook
  • Patent number: 10877509
    Abstract: A processor includes a plurality of processing cores; a frequency divider; and a synchronous first in first out (FIFO) buffer. The frequency divider frequency divides a first clock signal that is associated with a first clock domain to provide a second clock signal that is associated with a second clock domain. The synchronous FIFO buffer has a write port that is associated with the first clock domain and a read port that is associated with the second clock domain. The synchronous FIFO communicates the data between the first and second clock domains.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: December 29, 2020
    Assignee: INTEL CORPORATION
    Inventor: Ammon J. Christiansen
  • Patent number: 10872046
    Abstract: Network hardware of a computing device receives a network packet over a network to which the network hardware is connected. The network hardware determines that the network packet includes a power-cycling command. The network hardware, in response to determining that the network packet includes the power-cycling command, triggers a physical line between the network hardware and a power supply of the computing device. The power supply is connected to a power source and currently provides power from the power source to the computing device. In response to the network hardware triggering the physical line, the power supply interrupts providing the power to the computing device for a length of time to cause the computing device to restart and cold reboot.
    Type: Grant
    Filed: June 4, 2017
    Date of Patent: December 22, 2020
    Assignee: LENOVO Enterprise Solutions (Singapore) PTE. LTD
    Inventors: Fred Allison Bower, III, Caihong Zhang, Christopher Landon Wood
  • Patent number: 10860425
    Abstract: A method for recovering a basic input/output system (BIOS) image file of a computer system is provided. The method includes steps of: controlling a switch unit of the computer system to switch from a first state to a second state when the BIOS image file is to be updated; reading a current BIOS image file so as to store the same as a backup; controlling the switch unit to switch back to the first state; determining whether a command is received within a first predetermined time period when the BIOS image file is successfully updated to a new version of the BIOS image file; and when negative, controlling the switch unit to switch to the second state and writing the backup of the current version of the BIOS image file.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 8, 2020
    Assignee: MITAC COMPUTING TECHNOLOGY CORPORATION
    Inventor: Shun-Chieh Yang
  • Patent number: 10846099
    Abstract: Systems, methods, and software can be used to select a boot loader. In some aspects, a primary boot loader on an electronic device invokes a boot selector stored on a permanent memory storage on the electronic device. The boot selector selects a secondary boot loader stored on the electronic device. The selected secondary boot loader is executed to boot the electronic device.
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: November 24, 2020
    Assignee: BlackBerry Limited
    Inventors: Bryon Hummel, Rodney Derek Bylsma, Catalin Visinescu
  • Patent number: 10838479
    Abstract: A management device includes a processor that stores, in a second memory, power source information indicating first states of power sources of respective first electronic apparatuses included in an electronic apparatus group. The processor instructs, upon receiving a first instruction, the first electronic apparatuses identified by first apparatus information held in a first memory to transition the respective first states. The processor receives a second instruction to add a new electronic apparatus to the electronic apparatus group. The processor suppresses, in a case where any one of the first states is being transitioned, second apparatus information of the new electronic apparatus from being stored in the first memory. The processor stores the second apparatus information in the first memory in a case where transition of all the first states has been completed, and matches a second state of a power source of the new electronic apparatus with the first states.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: November 17, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Kouichi Tsukada, Kazumi Kojima
  • Patent number: 10838482
    Abstract: For power management in a disaggregated computing system, initial electrical power levels are distributed thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system. The voltage and the clock speed of respective processor cores within the set of processor cores are adjusted according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA).
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: November 17, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruchi Mahindru, John A. Bivens, Koushik K. Das, Min Li, HariGovind V. Ramasamy, Yaoping Ruan, Valentina Salapura, Eugen Schenfeld
  • Patent number: 10831252
    Abstract: Sub-components assembled into a computer are selected based on sub-component power efficiency levels (for example, low, medium, high) and/or anticipated usage of the computer. Multiple units of each type of sub-component (for example, a CPU) are tested to determine a power efficiency level of each unit. Computers in which sub-component efficiency levels are desired to match an overall computer efficiency level, receive sub-component units of corresponding efficiency level. Computers anticipated to run applications that make intensive use of a given type of sub-component receive the given units having a higher efficiency level. Computers anticipated to run applications that make little use of a given type of sub-component receive a physical unit having a lower efficiency level. Computers anticipated to run a wide variety of applications of no particular usage intensity for a given type of sub-component, receive a unit having an average efficiency level.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Eun Kyung Lee, Bilge Acun, Yoonho Park
  • Patent number: 10824187
    Abstract: A signal processing circuit includes: a clock input terminal configured to receive a master clock from outside: a signal processing part configured to perform a signal processing based on the master clock; an interface circuit configured to communicate with an external circuit; and a clock detection circuit configured to determine, using a serial clock received by the interface circuit, whether the master clock is input.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: November 3, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Mitsuteru Sakai
  • Patent number: 10824437
    Abstract: A management server exposes a web services interface through which managed clients that are not equipped with baseboard management controllers (“BMCs”) can submit management data at boot time. The firmware of the managed clients can receive management commands from the management server during boot time. The management server can also expose a web services interface to management clients through which the management clients can obtain the management data provided by the managed clients as if the management data were being provided through a BMC. The management server can also receive management commands from the management client computers for performance at the managed client computers. The management server queues the management commands for provision to the appropriate managed clients during the next boot of the managed clients.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: November 3, 2020
    Assignee: American Megatrends International, LLC
    Inventors: Stefano Righi, Madhan B. Santharam, Arun Subramanian Baskaran
  • Patent number: 10817305
    Abstract: An information handling system includes a memory and a central processing unit. The memory stores a boot image for a boot process of the information handling system. The central processing unit loads the boot image and executes the boot process. During the boot process, the central processing unit performs a pre-EFI initialization phase that configures a socket of the central processing unit during an auto-discovery of the socket, and stores the socket configuration in a memory.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: October 27, 2020
    Assignee: Dell Products, L.P.
    Inventor: Alberto David Perez Guevara
  • Patent number: 10795427
    Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 6, 2020
    Assignee: Apple Inc.
    Inventors: Hardik K. Doshi, Gopal Thirumalai Narayanan, Siddharth P. Shah, Joseph J. Castro, Craig S. Forbell, Christopher M. Aycock, Varaprasad V. Lingutla
  • Patent number: 10795423
    Abstract: An electronic apparatus having a function to omit part of initialization processing that is performed at the time of cold boot by using information held in a volatile storage device in returning from a power-saving state where power consumption is suppressed includes: a determination unit configured to determine, based on information indicating a connection state of a specific module of all the modules, whether to suspend supply of power to all modules of the electronic apparatus or to make a transition into the power-saving state where supply of power to at least the volatile storage device is maintained in response to an operation to turn off a power source by a user; and a power source control unit configured to control supply of power to each module of the electronic apparatus in accordance with the determination, and in activation processing in accordance with the function, part of initialization processing of the specific module is omitted.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 6, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Takahiro Yamashita
  • Patent number: 10796004
    Abstract: A system for performing coincident boot of computing devices having non-volatile memory and secure and non-secure partitions on the same System on Chip (SoC) or on a similarly capable computing device with secure division and separation of sensitive memory resources, secure protection of intellectual property during boot and post-boot, and support for secure interoperations between secure and non-secure states. The system packages components of the boot loader into a single signed and encrypted package. That package is loaded into the non-secure memory where it is verified before being extracted to the secure partition.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 6, 2020
    Assignee: Sequitur Labs Inc.
    Inventors: Philip Charles Davis, Philip Attfield, Michael Doyle, Michael Thomas Hendrick
  • Patent number: 10788853
    Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Maneesh Soni, Rajeev Suvarna, Nikunj Khare
  • Patent number: 10788883
    Abstract: A communications system and method provides power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: September 29, 2020
    Assignee: ARM Ltd
    Inventors: Edgar H. Callaway, Jr., Vasan Venkataraman, Brian Alan Nagel
  • Patent number: 10782763
    Abstract: A semiconductor device includes a voltage sensor which samples a power supply voltage at a speed faster than fluctuations in the power supply voltage and encodes the power supply voltage into a voltage code value. A voltage drop determination circuit detects a voltage drop based on the voltage code value, and a clock control circuit generates a clock. The clock control circuit stops the clock when the voltage drop determination circuit detects the voltage drop. The voltage drop determination circuit includes a prediction computation circuit which looks ahead a voltage value from a history of the voltage code value and predicts a variation value, and the prediction computation circuit includes a circuit for masking a prediction value if a differential value of the prediction value is continuously negative for a predetermined cycle.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: September 22, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yuko Kitaji, Kazuki Fukuoka, Ryo Mori, Toshifumi Uemura