Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract: A method and apparatus for managing power in a thermal couple aware system includes determining a candidate configuration mapping based upon one or more criteria, the candidate configuration mapping being a mapping of performance for a candidate configuration of processor sockets in the thermal couple aware system. The candidate configuration mapping is evaluated by comparing the candidate configuration mapping to a stored configuration. If the evaluated candidate configuration mapping provides a better metric than the stored configuration, the stored configuration is updated with the evaluated candidate configuration mapping, and programming instructions are executed in accordance with the candidate configuration mapping if no other configuration mappings are to be determined.

Abstract: An embedded multiprocessor system is provided that includes a multiprocessor system on a chip (SOC), a memory coupled to the multiprocessor SOC, the memory storing application software partitioned into an initial boot stage and at least one additional boot stage, and a secondary boot loader configured to boot load the initial boot stage on at least one processor of the multiprocessor SOC, wherein the initial boot stage begins executing and flow of data from the initial boot stage to the at least one additional boot stage is disabled, wherein the application software is configured to boot load a second boot stage of the at least one additional boot stage on at least one other processor of the multiprocessor SOC and to enable flow of data between the initial boot stage and the second boot stage.

Abstract: An electronic device, including a power source, power-consuming devices, a USB interface, a command receiver, a memory, and a controller, is provided. The controller forecasts at least one of the power-consuming devices to be used in one of a plurality of time segments, calculates a level of total operation power being sum of power required by the forecasted at least one of the power-consuming devices for the time segment with reference to values of power stored in the memory, and determine a level of the power to be delivered to an external device connected to the USB interface in the time segment based on the level of the total operation power and the level of the power capacity in the power source. The controller controls the power source to deliver the determined level of the power to the external device through the USB interface during the time segment.

Abstract: A power supplying method for a computer system is proposed. The computer system includes a first computer node, a first power supply unit corresponding to the first computer node, a second computer node, a second power supply unit corresponding to the second computer node, and a connection module electrically connected to the computer nodes and the power supply units. The power supplying method includes: detecting, by the first computer node, whether the second power supply unit operates abnormally; and upon detecting at least that the second power supply unit operates abnormally, controlling, by the first computer node, the first power supply unit to provide electric power to the second computer node through the connection module.

Abstract: A processor memory mapped boot system includes a processing system having a processor memory subsystem, and a memory system having at least one memory device. A Basic Input/Output System (BIOS) engine is coupled to the processing system and the memory system, and is configured to begin boot operations and detect a boot memory mode setting for the processor memory subsystem. The BIOS engine configures a memory space that includes the at least one memory device and the processor memory subsystem. In response to detecting the boot memory mode setting, the BIOS engine will configured the processor memory subsystem to provide a first memory region of the memory space. The BIOS engine will then complete boot operations utilizing the processor memory subsystem providing the first memory region of the memory space.

Abstract: A thermal manager manages programmable devices that include one or more accelerators. The thermal manager may be part of an accelerator manager that manages multiple accelerators in multiple programmable devices. The thermal manager monitors the temperature of a programmable device and casts out one or more accelerators when the temperature of the programmable device exceeds a threshold. Where there are multiple accelerator images that have different thermal effects for a given function the thermal manager may replace the cast out accelerator with another accelerator image for the same function that uses less power.

Abstract: Booting a virtual machine instance using remote direct memory access is provided. In response to beginning to receive pages of a predetermined set of pages corresponding to a requested image of a virtual machine from an image provider server, a boot process of an instance of the virtual machine is commenced while the received pages are written directly into a random-access memory (RAM) disk. The received pages are read from the RAM disk during the boot process of the instance of the virtual machine until transfer of the predetermined set of pages corresponding to the requested image is complete. The predetermined set of pages corresponding to the requested image are written to a local hard disk drive from the memory releasing memory usage. In response to completing the boot process, a RAM image is switched to a local hard disk drive image.

Abstract: An architecture for improving reliability of a multi-server system is provided. The hard disk backplane is provided with at least two hard disk modules, each of which includes a power supply isolation unit and a signal isolation unit. The power connection board is connected to the power supply isolation unit in each of the at least two hard disk modules, so that power supplies of the at least two hard disk module are isolated from each other. Each of the at least two server nodes is connected to at least one of the hard disks through a corresponding signal isolation unit. The server node, the signal isolation unit and the hard disk which are connected to each other form an isolated data communication group. Signal isolation units in any two of isolated data communication groups belong to different hard disk modules.

Abstract: Disclosed is an electronic device including a battery; an interface that receives an external power; a system circuit including a processor; and a power management circuit, wherein the power management circuit is configured to detect an input of the external power through the interface; identify a voltage of the battery in response to the detection of the input of the external power; when the voltage of the battery belongs to a first designated voltage range, avoid charging the battery using the input external power and supply the input external power to the system circuit; and when the voltage of the battery belongs to a second designated voltage range, charge the battery using at least some of the input external power.

Abstract: An embodiment of a semiconductor package apparatus may include technology to determine respective priority levels for one or more boot time events, determine an amount of execution time for the one or more boot time events, and automatically adjust a timer based on the amount of execution time and the priority levels for the one or more boot time events. Other embodiments are disclosed and claimed.

Abstract: A computing device includes a processor having a plurality of cores, a core translation component, and a core assignment component. The core translation component provides a set of registers, one register for each core of the multiple processor cores. The core assignment component includes components to provide a core index to each of the registers of the core translation component according to a core assignment scheme during processor initialization. Process instructions from an operating system are transferred to a respective core based on the core indices.

Abstract: A storage controller communicates with an external device including a submission queue and a completion queue. An operation method of the storage controller includes receiving a notification associated with a command from the external device, based on a first clock, fetching the command from the submission queue, based on a second clock, performing an operation corresponding to the fetched command, based on a third clock, writing completion information to the completion queue, based on a fourth clock, and transmitting an interrupt signal to the external device, based on a fifth clock. Each of the first clock to the fifth clock is selectively activated depending on each operation phase.

Abstract: A method, apparatus and computer program are provided for allocating power amount a plurality of computing devices. The method includes determining a current power capping amount for each of a plurality of computing devices and obtaining a current power usage of each computing device. The method further includes determining, for each computing device, an updated power capping amount based on whether or not the current power usage of the computing device has reached the current power capping amount of the computing device during a current period of time. The updated power capping amount is allocated to the respective computing devices, and a power supply is caused to deliver power to each computing device in an amount up to the updated power capping amount that has been allocated to the respective computing device.

Abstract: Techniques relating to communicating system events in universal serial bus (USB) power delivery (PD) devices are described. In an example, a USB PD controller receives a notification of a system event in a first device associated with the USB PD controller, the system event being based on one of a change in machine state of the first device and occurrence of a user interaction event in the first device. A PD protocol based message, indicative of the system event in the first device, is generated. The PD protocol based message provides for activation of a predefined profile setting in a second device, wherein the second device is to interface with the first device through the USB PD controller.

Abstract: A method for adjusting operation parameters of a computer system based on power consumption of the computer system is disclosed. During a power state transition of the computer system, a voltage level of a power supply signal may be sampled at a plurality of time points to generate a multiple voltage level samples. A voltage level of a selected one of the multiple voltage level samples may be adjusted using a particular coefficient of multiple coefficients to generate an updated voltage level sample. A power consumption of the computer system may be determined using the updated voltage level sample, and based on the power consumption, at least one operation parameter of the computer system may be adjusted.

Abstract: A processor includes a plurality of processing cores; a frequency divider; and a synchronous first in first out (FIFO) buffer. The frequency divider frequency divides a first clock signal that is associated with a first clock domain to provide a second clock signal that is associated with a second clock domain. The synchronous FIFO buffer has a write port that is associated with the first clock domain and a read port that is associated with the second clock domain. The synchronous FIFO communicates the data between the first and second clock domains.

Abstract: A method for creating devices facilitating secure data transmission, storage and key management. At least two devices are each comprised of at least part of a physically unclonable function unit originally shared by the at least two devices on a single, monolithic original integrated circuit. The process includes physically segmenting the shared physically unclonable function unit between the at least two devices. The at least two devices which share the single, monolithic integrated circuit are physically separated into individual device units.

Abstract: Network hardware of a computing device receives a network packet over a network to which the network hardware is connected. The network hardware determines that the network packet includes a power-cycling command. The network hardware, in response to determining that the network packet includes the power-cycling command, triggers a physical line between the network hardware and a power supply of the computing device. The power supply is connected to a power source and currently provides power from the power source to the computing device. In response to the network hardware triggering the physical line, the power supply interrupts providing the power to the computing device for a length of time to cause the computing device to restart and cold reboot.

Abstract: A method for recovering a basic input/output system (BIOS) image file of a computer system is provided. The method includes steps of: controlling a switch unit of the computer system to switch from a first state to a second state when the BIOS image file is to be updated; reading a current BIOS image file so as to store the same as a backup; controlling the switch unit to switch back to the first state; determining whether a command is received within a first predetermined time period when the BIOS image file is successfully updated to a new version of the BIOS image file; and when negative, controlling the switch unit to switch to the second state and writing the backup of the current version of the BIOS image file.