Abstract: Systems, methods, and software can be used to select a boot loader. In some aspects, a primary boot loader on an electronic device invokes a boot selector stored on a permanent memory storage on the electronic device. The boot selector selects a secondary boot loader stored on the electronic device. The selected secondary boot loader is executed to boot the electronic device.

Abstract: For power management in a disaggregated computing system, initial electrical power levels are distributed thereby allocating a voltage and a clock speed to each one of a set of processor cores in the disaggregated computing system. The voltage and the clock speed of respective processor cores within the set of processor cores are adjusted according to a workload priority of respective workloads performed by each respective one of the processor cores, wherein the workload priority is assigned based upon a service level agreement (SLA).

Abstract: A management device includes a processor that stores, in a second memory, power source information indicating first states of power sources of respective first electronic apparatuses included in an electronic apparatus group. The processor instructs, upon receiving a first instruction, the first electronic apparatuses identified by first apparatus information held in a first memory to transition the respective first states. The processor receives a second instruction to add a new electronic apparatus to the electronic apparatus group. The processor suppresses, in a case where any one of the first states is being transitioned, second apparatus information of the new electronic apparatus from being stored in the first memory. The processor stores the second apparatus information in the first memory in a case where transition of all the first states has been completed, and matches a second state of a power source of the new electronic apparatus with the first states.

Abstract: Sub-components assembled into a computer are selected based on sub-component power efficiency levels (for example, low, medium, high) and/or anticipated usage of the computer. Multiple units of each type of sub-component (for example, a CPU) are tested to determine a power efficiency level of each unit. Computers in which sub-component efficiency levels are desired to match an overall computer efficiency level, receive sub-component units of corresponding efficiency level. Computers anticipated to run applications that make intensive use of a given type of sub-component receive the given units having a higher efficiency level. Computers anticipated to run applications that make little use of a given type of sub-component receive a physical unit having a lower efficiency level. Computers anticipated to run a wide variety of applications of no particular usage intensity for a given type of sub-component, receive a unit having an average efficiency level.

Abstract: A signal processing circuit includes: a clock input terminal configured to receive a master clock from outside: a signal processing part configured to perform a signal processing based on the master clock; an interface circuit configured to communicate with an external circuit; and a clock detection circuit configured to determine, using a serial clock received by the interface circuit, whether the master clock is input.

Abstract: A management server exposes a web services interface through which managed clients that are not equipped with baseboard management controllers (“BMCs”) can submit management data at boot time. The firmware of the managed clients can receive management commands from the management server during boot time. The management server can also expose a web services interface to management clients through which the management clients can obtain the management data provided by the managed clients as if the management data were being provided through a BMC. The management server can also receive management commands from the management client computers for performance at the managed client computers. The management server queues the management commands for provision to the appropriate managed clients during the next boot of the managed clients.

Abstract: An information handling system includes a memory and a central processing unit. The memory stores a boot image for a boot process of the information handling system. The central processing unit loads the boot image and executes the boot process. During the boot process, the central processing unit performs a pre-EFI initialization phase that configures a socket of the central processing unit during an auto-discovery of the socket, and stores the socket configuration in a memory.

Abstract: A system for performing coincident boot of computing devices having non-volatile memory and secure and non-secure partitions on the same System on Chip (SoC) or on a similarly capable computing device with secure division and separation of sensitive memory resources, secure protection of intellectual property during boot and post-boot, and support for secure interoperations between secure and non-secure states. The system packages components of the boot loader into a single signed and encrypted package. That package is loaded into the non-secure memory where it is verified before being extracted to the secure partition.

Abstract: An electronic apparatus having a function to omit part of initialization processing that is performed at the time of cold boot by using information held in a volatile storage device in returning from a power-saving state where power consumption is suppressed includes: a determination unit configured to determine, based on information indicating a connection state of a specific module of all the modules, whether to suspend supply of power to all modules of the electronic apparatus or to make a transition into the power-saving state where supply of power to at least the volatile storage device is maintained in response to an operation to turn off a power source by a user; and a power source control unit configured to control supply of power to each module of the electronic apparatus in accordance with the determination, and in activation processing in accordance with the function, part of initialization processing of the specific module is omitted.

Abstract: A method from managing power state transitions in a computing system is disclosed. A processor may initiate a change in power state from a first initial power state to a first new power state and, in response to initiating the change, send an initial notification to a system integrated circuit using a first communication channel, and deactivate the first communication based on responses to the initial notification. The processor may enter the first new power state in response to the deactivation of the first communication channel, and send a final notification to a management controller using a second communication channel. The management controller may send a message to the system integrated circuit upon receiving the final notification. The system integrated circuit may then transition from a second initial power state to a second new power state based on the message.

Abstract: A communications system and method provides power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.

Abstract: Disclosed examples include interrupt handling circuitry and methods for managing interrupts of a fast clock domain circuit operated according to a first clock signal by a slow clock domain circuit operated according to a second clock signal in which an interrupt generator circuit generates an interrupt input signal synchronized to the second clock signal, and an interrupt clear circuit selectively resets the interrupt generator circuit in response to an acknowledgment signal from the first circuit asynchronously with respect to the second clock signal.

Abstract: An application processor includes a main central processing device that operates based on an external main clock signal received from at least one external clock source when the application processor is in an active mode, at least one internal clock source that generates an internal clock signal, and a sensor sub-system that processes sensing-data received from at least one sensor module on a predetermined cycle when the application processor is in the active mode or a sleep mode, and that operates based on the internal clock signal or an external sub clock signal received from the external clock source depending on an operating speed required for processing the sensing-data.

Abstract: A semiconductor device includes a voltage sensor which samples a power supply voltage at a speed faster than fluctuations in the power supply voltage and encodes the power supply voltage into a voltage code value. A voltage drop determination circuit detects a voltage drop based on the voltage code value, and a clock control circuit generates a clock. The clock control circuit stops the clock when the voltage drop determination circuit detects the voltage drop. The voltage drop determination circuit includes a prediction computation circuit which looks ahead a voltage value from a history of the voltage code value and predicts a variation value, and the prediction computation circuit includes a circuit for masking a prediction value if a differential value of the prediction value is continuously negative for a predetermined cycle.

Abstract: Systems and methods for automated device setting customization based on user characteristic data are disclosed. In embodiments, a computer-implemented method comprises: receiving, by a computing device, real-time user characteristic data; determining whether the user is a known user of the computing device based on the real-time user characteristic data; identifying one or more characteristics of the user based on the real-time user characteristic data; determining a statistical confidence level of the one or more characteristics of the user; determining that the statistical confidence level meets a predetermined threshold value; and automatically changing a plurality of user configurable settings of the computing device based on the one or more characteristics of the user and in response to the determining that the statistical confidence level meets the predetermined threshold value.

Abstract: A calibration controller of a receiving chip learns a difference between a first clock phase of an input clock for controlling inputs on a data path to a buffer of the receiving chip at a clock boundary and a second clock phase of a chip clock for controlling outputs from the buffer on the data path at the clock boundary. The calibration controller dynamically adjusts a phase of a reference clock driving a phase locked loop that outputs the chip clock to adjust the second clock phase of the chip clock with respect to the first clock phase to minimize a latency on the data path at the clock boundary to a half a cycle granularity.

Abstract: A system and method configured with an electronic device to enable prediction-based power management by providing direct transition to a lower power state such that overall energy consumption is reduced. The system and method includes an idleness information recording module configured to, using a power management agent, non-intrusively observe and record usage and idleness information of the electronic device, a learning module configured to, using a neural network operatively coupled with the power management agent, conduct deep learning of idleness patterns of the electronic device, a prediction module configured to predict future idleness of the electronic device based on the deep learning of the idleness patterns, and a prediction-based lower power state transfer module configured to directly transition the electronic device to lower power state based on the predicted future idleness.

Abstract: Systems, apparatuses, and methods for intentionally delaying servicing of interrupts in a computing system are disclosed. A computing system includes a processor that services interrupts generated by components of the computing system. An interrupt controller detects a received interrupt and intentionally delays servicing of the interrupt depending on various conditions. If the interrupt is a first type of interrupt and the processor is in a first power state, servicing of the interrupt is delayed by a first period of time. If the interrupt corresponds to the first type of interrupt and the processor is in a second power state, servicing of the interrupt is delayed for a period of time that is longer than the first period of time. If a non-maskable interrupt is received before expiration of either the first or second period of time, then servicing of any previously delayed interrupts is allowed to proceed.

Abstract: A microcontroller includes a core and a unit for managing the power supply of the core that includes an input for receiving an external signal indicating a leaving of a stand-by mode of operation. A signal intercepting unit intercepts the external signal and transmitting it with a delay to the unit for managing.

Abstract: A system includes an ARM core processor, a programmable regulator, a compiler, and a control unit, where the compiler uses a performance association outcome to generate a 2-bit regulator control values encoded into each individual instruction. The system can provide associative low power operation where instructions govern the operation of on-chip regulators or clock generator in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme with energy models are formulated for deriving the energy efficiency of the associative operation. An integrated voltage regulator or clock generator is dynamically controlled based on instructions existing in the current pipeline stages leading to additional power saving. A compiler optimization strategy can further improve the energy efficiency.