Abstract: An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in storage nodes of a pipeline element and the identical routing signal bypassing the pipeline element. A programming element may access the storage nodes of the pipeline elements for write operations and, if desired, for read operations. For example, the programming element may perform write operations to initialize the storage nodes to a known state during power-up operations or to reset the pipeline element. In addition, the programming element may perform reed operations for debug and testing purposes.

Abstract: A low-latency network interface and complementary data management protocols are disclosed in this specification. The data management protocols reduce dedicated control exchanges between the network interface and a corresponding host computing system by consolidating control data with network data. The network interface may also facilitate port forwarding and data logging without an external network switch.

Abstract: Method for connecting mass storage device(s) with data connection device(s) connecting to data port(s) with the same data interface type(s) as that of the mass storage device(s) for data transmission and with power connection device(s) connecting to power port(s), for power supply, on a bus of technologies with power management capabilities and facilities in computer-related or computer-controlled or operating-system-controlled machines or devices for using and swapping the mass storage device(s).

Abstract: The system comprises a device, the device comprising a physical port. The device is configured to communicate with a controller through a communication medium. The controller is situated on a circuit board. The physical port is not configured to communicate with the communication medium. The device is also configured to communicate with a processor through the circuit board, but the physical port is not configured to communicate with the processor through the circuit board. The device is additionally configured to create a first packet comprising information corresponding to first device information. The first device information is formatted in a protocol associated with the physical port. The device is further configured to transmit the first packet to the controller through the communication medium.

Abstract: By integrating multiple electronic devices, it is possible to increase the functionality of the devices individually. For example it is possible to improve media playback functionality, create media playlists “on-the-go” and to use a first device power supply to charge the power supply of the second device. By integrating the devices, it is possible to address some of the shortcomings of devices that are decreasing in size with increasing power requirements, while still maintaining the advantages that these devices offer.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer operations. In one embodiment, the computer implemented method includes the steps of receiving a request from an input/output (I/O) device to perform a data transfer operation between the I/O device and a memory, generating an entry in an input/output memory management unit (IOMMU) corresponding to the data transfer operation, wherein the entry in the IOMMU includes at least an indication of a processor chip that corresponds to the memory of the data transfer operation, monitoring the data transfer operation between the I/O device and the memory, determining statistics corresponding to the monitored data transfer operation, wherein the determined statistics include at least: the I/O device that performed the data transfer operation, the processor chip that corresponds to the memory of the data transfer operation, and an amount of data transferred.

Abstract: A device is provided that has a bus including a first line and a second line. A first set of devices are coupled to the bus and, in a first mode of operation, configured to use the first line for data transmissions and use the second line for a first clock signal. One or more additional lines are connected between two or more of the devices in the first set of devices for transmitting signaling between the two or more devices. A second set of devices are configured to use the bus and at least one of the additional lines for data transmissions in a second mode of operation, where in the second mode of operation symbols are encoded across the first line, the second line, and the at least one of the additional lines.

Abstract: Time-critical actions of peripherals sharing a synchronous serial bus can be coordinated flexibly in real time by transmitting the messages through the bus well in advance of the scheduled execution time rather than “just in time.” The messages include an action code addressed to the peripheral's shadow register and a time-to-strobe, measured in bus-clock cycles, calculated by a time protocol engine in the system controller and addressed to the peripheral's counting register. The action code is stored in the shadow register while the counting register counts up or down to the time-to-strobe using the bus-clock signal. When the count reaches zero, the action code is written to the function-control register, triggering immediate execution of the action. Because the time-to-strobe can be any number of clock cycles within the counting register's capacity, the transmission timing is decoupled from the execution timing, relaxing transmission-timing constraints.

Abstract: A system includes a cut-through buffer operable to be asynchronously read while being written at different clock frequencies. The system also includes a controller operatively connected to the cut-through buffer. The controller is operable to write one or more values into the cut-through buffer in a first clock domain and compare a number of values written into the cut-through buffer to a notification threshold. A notification indicator is passed from the first clock domain to a second clock domain based on determining that the number of values written into the cut-through buffer meets the notification threshold. Based on receiving the notification indicator, the cut-through buffer is read from the second clock domain continuously without pausing until the one or more values are retrieved and any additional values written to the cut-through buffer during the reading of the one or more values are retrieved.

Abstract: A remote resource access method and a switching device are provided. According to the remote resource access method, when a computer system access the remote physical resource device, after obtaining a first access message, including a virtual address of a virtual resource device, from a computing node in the computer system, the switching device converts the first access message into a second access message based on a physical address of a physical resource device corresponding to the virtual address of the virtual resource device. Then, the switching device sends the second access message to the remote physical resource device corresponding to the physical address using a network, thereby implementing the data transmission between the local computer system and the remote physical resource device.

Abstract: A distributed computing architecture for executing at least first and second computing operations executed in parallel on a set of data, can include a plurality of servers, including first servers that each include at least one central processing unit (CPU), and at least one offload processing module coupled to CPU by a bus. Each offload processing module can include computation elements. The computation elements can be configured to operate as a virtual switch, and to execute the second computing operations on first processed data to generate second processed data. The virtual switches can form a switch fabric for exchanging data between the offload processing modules. The second computing operations are executed on a plurality of the offload processing modules in parallel.

Abstract: In a method for allocating addresses in a CAN network having at least one master bus user and at least one slave bus user, the master bus user initiates the address allocation via a query message that is arranged for all bus users. Slave bus users which have already been assigned an address respond to this query message by transmitting a message at their assigned address. Slave bus users which have not yet been assigned an address take measures in response to this query message to be able to transmit on the bus without collisions, and transmit their serial number to the master bus user using these measures. At least the slave bus users which have not yet been assigned an address are assigned a suitable address by the master after receipt of the serial number, and use this address for further communication on the bus.

Abstract: This application relates to methods and apparatus for transfer of data between a host device (400) and a peripheral device (300) via a USB Type-C connector (100; 304) of the host device. A data controller is described that has a path controller (309, 310; 706) for establishing signal paths between circuitry of the host device and contacts (101) of said USB Type-C connector. The path controller is operable in at least first and second modes. In the first mode the path controller establishes separate signal paths to each of at least first, second, third and fourth contacts (A6, A7, B6, B7) of the USB Type-C connector and a plurality of the established signal paths are for transfer of analog audio data. In the second mode the path controller establishes a pair of signal paths to only a subset of said first to fourth contacts to provide a differential digital data path.

Abstract: Provided is a terminal for controlling an external device, not equipped with its own memory or controller, connected to the terminal. The portable terminal, when being connected to at least one external device, changes its setting with an extracted setting data matching the connected external device. Accordingly, the connected external device in a connection state to the portable terminal performs corresponding operations under control of the portable terminal.

Abstract: An enhanced multi chip package (eMCP) is provided including a unified memory controller. The UMC is configured to manage different types of memory, such as NAND flash memory and DRAM on the eMCP. The UMC provides storage memory management, DRAM management, DRAM accessibility for storage memory management, and storage memory accessibility for DRAM management. The UMC also facilitates direct data copying from DRAM to storage memory and vice versa. The direct copying may be initiated by the UMC without interaction from a host, or may be initiated by a host.

Abstract: A bus interface system is disclosed that includes a master bus controller and a slave bus controller that are coupled by a bus line. The slave bus controller includes a decoder that allows for data to be transmitted along just the bus line. The decoder includes an oscillator, a first counter, and a comparison circuit. The oscillator is configured to be enabled by data pulses defined by the input data signal and generate oscillation pulses while enabled. The first counts the oscillation pulses and indicates a number of the oscillation pulses generated during a time slot. The comparison circuit is configured to this number with a reference number and generate a data output that represents a first logical value in response to the number being greater than the reference parameter and represents a second logical value in response to the number being less than the reference parameter.

Abstract: A memory system comprises a memory device coupled to a memory controller, the memory controller for receiving one or more memory requests from one or more core devices via an interconnect bus. The memory controller tracks utilization of the interconnect bus by tracking a selection of the one or more memory requests with fetched data from the one or more memory devices and waiting for scheduling to return on the interconnect bus during a time window. The memory controller, responsive to detecting utilization of the interconnect bus during the time window reaches a memory utilization threshold, dynamically selects a reduced read data size for a size of the fetched data to be returned with at least one read request from among the selection of one or more memory requests, the reduced data size selected from among at least two read data size options for the at least one read request of a maximum read data size and the reduced read data size that is less than the maximum read data size.

Abstract: A method and system for assigning slot addresses to modules in an industrial control system is disclosed. The modules are set up in a daisy chain topology. On power-up, a first module in the chain reads its slot address from a user configurable input or sets its slot address to a default value. The first module communicates to its immediate right neighbor using a special, one-hop message. The neighboring modules communicate to receive each other's information. The first module then sets an enable signal between the modules and sends a slot number to the neighbor in a firmware message. The neighbor checks if the enable signal is set and verifies that the slot number is a valid slot number. If so, then the neighboring module accepts the slot and repeats the same procedure to its next immediate neighbor, and so on until the last module.

Abstract: A system for enabling input/out virtualization for a device is disclosed. In one embodiment, the system includes a plurality of host CPUs; a multi-root switch connected to each of the plurality of host CPUs via respective buses; and an inline PCI virtualizing device connected to the multi-root switch via a front-side bus and the device via a back-side bus, the inline PCI virtualizing device including a plurality sets of registers, each of the plurality sets of registers accessible by a corresponding host CPU of the plurality of host CPUs and implementing functionalities of the device.

Abstract: Examples relate to extending hardware support for sensors embedded in peripherals. In some examples, a driver is used to determine that a peripheral device includes a sensor in response to the peripheral device being attached to a mobile computing device, where the driver is preloaded in an operating system kernel of the mobile computing device. Next, a list of supported hardware features is updated to include a peripheral hardware feature that is provided by a sensor of the peripheral device, and the list of supported hardware features is sent to an application store server. At this stage, a list of available applications that are compatible with the list of supported hardware features is received from the application store server.