Abstract: The present application is directed to a television device and a control method therefor. The television device comprises an SOC chip, a DFP interface thereof being connected to a switch module via a USB D+/D? differential pair, and the USB D+/D? differential pair between the DFP interface and the switch module being a first channel; a USB Type-C interface main control module provided with a UFP interface, the UFP interface being connected to the switch module via a USB D+/D? differential pair, and the USB D+/D? differential pair between the UFP interface and the switch module being a second channel; and a USB Type-C interface connected to the switch module via a USB D+/D? differential pair. The USB Type-C interface main control module is also connected to the switch module via a control signal line.

Abstract: In example implementations, an apparatus is provided. The apparatus includes a first interface, an upstream device detector, a second interface, and a processor. The first interface receives a multi-channel connection. The upstream device detector is to detect a connection to external graphical processor unit (eGPU) via the first interface. The second interface is to connect a peripheral device that transmit data over the multi-channel connection via the first interface through the eGPU and to a host computer. The processor disables a portion of the multi-channel connection on the first interface when the upstream device detector detects the connection to the eGPU.

Abstract: In one embodiment, an apparatus includes an input/output (I/O) circuit to communicate information at a selected voltage via an interconnect to which a plurality of devices may be coupled, and a host controller to couple to the interconnect. The host controller may include a supply voltage policy control circuit to initiate a supply voltage policy exchange with a first device to obtain a first supply voltage capability of the first device and to cause the I/O circuit and the first device to be configured to communicate via the interconnect at a first supply voltage based on the first supply voltage capability. Other embodiments are described and claimed.

Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.

Abstract: A method for controlling data transmission mode of an SD memory card device, which at least operates under an SD mode, includes: sending a first power signal from an electronic device to the SD memory card device via pin VDD1 to control and make the SD memory card device enter an initial state; and, sending a second power signal via one of a pin VDD2 and a pin VDD3 to the SD memory card device, to control and make the SD memory card device enter an Linkup state of a PCIe mode wherein a voltage level of the second power signal is lower than a voltage level of the first power signal.

Abstract: A storage control system receives an I/O request from a client for accessing storage resources that are logically divided into device groups, and determines a resource token request value associated with the I/O request and a target device group to which the I/O request is directed. The storage control system determines a number of allowed resource tokens to allocate to the client as a function of (i) the resource token request value, (ii) a sum total of resource tokens requested by other clients for accessing the target device group, and (iii) a total amount of resource tokens currently allocated to the target device group to which the I/O request is directed. The storage control system sends the determined number of allowed resource tokens to the client to thereby enable the client to limit a number of inflight I/O requests that the client issues to the storage control system.

Abstract: An apparatus includes a plurality of output ports and a processor. The output ports may each be configured to connect to a respective trigger device and generate an output signal to activate the respective trigger device. The processor may be configured to determine a number of the trigger devices connected to the output ports, determine a timing between each of the number of the trigger devices connected, convert the timing for each of the trigger devices to fit a standard timing using offset values specific to each of the trigger devices and perform a trigger routine to trigger the output signal for each of the trigger devices connected. The trigger routine may activate each of the trigger devices connected according to an event. The offset values may delay triggering the trigger devices to ensure that the trigger devices are sequentially activated at intervals that correspond consistently with the standard timing.

Abstract: A control device is used to adjust an output voltage of a voltage generator, and includes a master circuit, a slave circuit, and a power-scaling control circuit. The master circuit is coupled to a first bus. The slave circuit is coupled to a second bus. In a normal mode, the first and second buses are connected to each other via the power-scaling control circuit, the master circuit accesses the slave circuit via the first and second buses. In an adjustment mode, the power-scaling control circuit controls the master circuit to stop accessing the slave circuit, and the power-scaling control circuit adjusts the output voltage. When the master circuit sends a trigger signal, the power-scaling control circuit enters the adjustment mode. When the master circuit does not send the trigger signal, the power-scaling control circuit enters the normal mode.

Abstract: Described herein are nodes, sub-systems and systems of nodes for use in a dynamic node based computer. In some embodiments, nodes include: one or more signal receivers for detecting or receiving one or more input signals from one or more signal sources, one or more signal transmitters for selectively connecting and transmitting signals to one or more other nodes; and a threshold device configured to control the selective operation of the signal transmitter based on a threshold derived from one or more characteristics of the input signals. More complex variations of the nodes include the addition of threshold manipulation devices, signal amplifiers or dampeners, control devices, or computational devices. Also described herein are machines or devices built from one or more such nodes.

Abstract: Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates over a multi-drop bus connected to multiple electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to execute the activity.

Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.

Abstract: A data processing apparatus includes a power-source controller, a data processing device, a physical-layer section, a communication controller, and a state controller. The power-source controller controls a first power-source setting and a second power-source setting. The second power-source setting causes less electric power consumption than the first power-source setting. The communication controller performs the communication with the data processing device through a predetermined communication path and the physical-layer section under the first power-source setting. The communication controller stops the communication with the data processing device through the communication path and the physical-layer section under the second power-source setting. The state controller maintains the second communication state with respect to the data processing device side of the communication path while electric power supply to the physical-layer section is reduced under the second power-source setting.

Abstract: In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

Abstract: An information handling system may include a basic input/output system (BIOS), a management controller configured to provide out-of-band management of the information handling system, a plurality of communications bus root complex ports, and a storage backplane having a plurality of slots configured to receive respective storage resources. The information handling system may be configured to: store, at the management controller, an initial data structure containing a correspondence between the plurality of communications bus root complex ports and the plurality of slots; transmit, from the BIOS to the management controller, information regarding bus numbers for a plurality of enumerated information handling resources coupled to the communications bus; and determine, by the management controller, a correspondence between the bus numbers and the plurality of slots.

Abstract: Provided is a terminal for controlling an external device, not equipped with its own memory or controller, connected to the terminal. The portable terminal, when being connected to at least one external device, changes its setting with an extracted setting data matching the connected external device. Accordingly, the connected external device in a connection state to the portable terminal performs corresponding operations under control of the portable terminal.

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

Abstract: A resource request is received by a network device from a virtual machine running on a host. The resource request includes a requested resource size. The network device allocates resources of the network device in response to the resource request. A resource response is sent by the network device to the virtual machine that generated the resource request. The resource response includes a location of the allocated resource.

Abstract: A method for configuring a controller in a master control chip can include operations such as: a controller is configured according to a sampling rate, a bit width occupied by data transmission of at least one peripheral and the number of the at least one peripheral plugged into an interface corresponding to the controller; and data transmitted by the at least one peripheral plugged into the interface is received through the configured controller. A configuration parameter of the controller is reconfigured, and then the peripheral may be connected to the interface at timing generated by the controller and the data transmitted by the at least one peripheral is acquired, thereby increasing the types of peripherals supported by the master control chip, and increasing the number of peripherals that can be plugged into the master control chip.

Abstract: A device can include a server that includes a host processor and at least one hardware acceleration (hwa) module having at least one computing element formed thereon, the at least one computing element including processing circuits configured to execute a plurality of processes, first memory circuits, second memory circuits, and a data transfer fabric configured to enable data transfers between the processing circuits and the first and second memory circuits; wherein the at least one computing element is configured to transfer data to, or receive data from, any of: the processing circuits, the first memory circuits, the second memory circuits, or other computing elements coupled to the data transfer fabric.

Abstract: Aspects of the present disclosure provide for a system. In at least some examples, the system includes an embedded Universal Serial Bus 2 (eUSB2) device having a first receiver and a first transmitter, a processor, a second transmitter coupled to the processor, a second receiver coupled to the processor, a drive low circuit coupled to the processor second transmitter, and differential signal lines having a length greater than ten inches. The differential signal lines are coupled at a first end to the first receiver and the first transmitter and at a second end to the second transmitter and the second receiver. The processor is configured to control the drive low circuit to drive the differential signal lines low with a logic ‘0’ to cause the first receiver to receive the logic ‘0’ and a value of a signal present on the differential signal lines to reach about 0 volts.