Abstract: A data processing system is implemented with a backup PCI Express system, which is able to take over as the primary PCI Express system for ensuring that the endpoint devices continue to function in a desired manner when the initial primary root complex is no longer functioning correctly. Each of the endpoint devices is coupled to the initial primary root complex and a backup root complex through a multiplexer. When a failure of the initial primary root complex is detected, the backup root complex signals each multiplexer to switch the communication of data from occurring between the initial primary root complex and the endpoint devices to then occur between the backup root complex and the endpoint devices.

Abstract: A method and system is provided for pre-deployment performance estimation of input-output intensive workloads. Particularly, the present application provides a method and system for predicting the performance of input-output intensive distributed enterprise application on multiple storage devices without deploying the application and the complete database in the target environment. The present method comprises of generating the input-output traces of an application on a source system with varying concurrencies; replaying the generated traces from the source system on a target system where application needs to be migrated; gathering performance data in the form of resource utilization, through-put and response time from the target system; extrapolating the data gathered from the target system in order to accurately predict the performance of multi-threaded input-output intensive applications in the target system for higher concurrencies.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: Embodiments of a bus interface system are disclosed. In one embodiment, the bus interface system includes a master bus controller and a slave bus controller coupled to a bus line. The master bus controller is configured to generate a first set of data pulses along the bus line representing a payload segment. The slave bus controller is configured to decode the first set of data pulses representing the payload segment into a decoded payload segment. The slave bus controller is then configured to perform a first error check on the decoded payload segment. Furthermore, the slave bus controller is configured to generate an acknowledgment signal along the bus line so that the acknowledgement signal indicates that the decoded payload segment passed the first error check. In this manner, the master bus controller can determine that the slave bus controller received an accurate copy of the payload segment.

Abstract: Embodiments of bus interface systems are disclosed. In one embodiment, a bus interface system includes a master bus controller and a slave bus controller coupled along a bus line. The master bus controller is configured to generate an input data signal that is received by the slave bus controller along the bus line. The slave bus controller includes power conversion circuitry configured to convert the input data signal from the master bus controller into a supply voltage. By providing the power conversion circuitry, the slave bus controller is powered using the input data signal and without requiring an additional bus line to transfer a supply voltage to the slave bus controller.

Abstract: Systems, methods, and apparatus for improving bus latency are described. A method performed at a device coupled to a serial bus includes using a dynamic identifier in a first transaction conducted over a first serial bus. The dynamic identifier includes unique identifier and variable identifier portions. The device participates in a sequence of bus arbitrations until the slave device gains access to the first serial bus or a second serial bus. The value of the variable identifier portion may be increased after each bus arbitration that does not result in a grant of access to the first serial bus, and cleared after each bus arbitration that results in a grant of access to the first serial bus. A second transaction may be conducted over the first serial bus after gaining access to the first serial bus. The value of the dynamic identifier defines slave device priority for bus arbitrations.

Abstract: An Integrated circuit (IC) device accommodating a circuit and associated control module, being operative to determine an apparatus characteristic in accordance with one out of few selectable characteristics. The circuit is operative in conjunction with more than three of a plurality of external passive circuits corresponding to the plurality of apparatus characteristics, and includes (N?1) digital I/O pins. The control module is operative to: (i) in response to a series of triggering signals, generate samples of the digital I/O pin's state that correspond to a plurality of different sequences of states when each of the plurality of external circuits is respectively applied to the pin and (ii) determining, from the samples, which of the plurality of different sequences of states has occurred that corresponds to the individual external circuit that has been applied to the pin; and (iii) determining an individual apparatus characteristic which corresponds to the determined sequence.

Abstract: The present disclosure provides new methods and systems for input/output command rebalancing in virtualized computer systems. For example, an I/O command may be received by a rebalancer from a virtual queue in a container. The container may be in a first virtual machine. A second I/O command may be received from a second virtual queue in a second container which may be located in a second virtual machine. The rebalancer may detect a priority of the first I/O command and a priority of the second I/O command. The rebalancer may then assign an updated priority each I/O command based on a quantity of virtual queues in the virtual machine of origin and a quantity of I/O commands in the virtual queue of origin. The rebalancer may dispatch the I/O commands to a physical queue.

Abstract: Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

Abstract: A system includes a non-programmable bus master. The non-programmable bus master includes a memory protection unit (MPU) to operate in a first configuration with a first set of access permissions and a second configuration with a second set of access permissions, and hardware logic. The hardware logic executes a first task and a second task. The tasks generate transactions and the hardware logic switches between executing the first and second tasks. The hardware logic also causes the MPU to operate in the first configuration when the hardware logic executes the first task and causes the MPU to operate in the second configuration when the hardware logic executes the second task.

Abstract: A server system and a method for detecting a transmission mode of the server system are provided. The storage system includes a control device and a storage back plane. The storage back plane includes a non-volatile memory module having mode information. When the control device is plugged into the storage back plane, the control device obtains the mode information of the storage back plane, determines whether the transmission mode of the control device matches the mode information, and decides whether to send a first prompt signal according to whether the transmission mode of the control device matches the mode information.

Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

Abstract: Techniques provide for hardware accelerated data movement between main memory and an on-chip data movement system that comprises multiple core processors that operate on the tabular data. The tabular data is moved to or from the scratch pad memories of the core processors. While the data is in-flight, the data may be manipulated by data manipulation operations. The data movement system includes multiple data movement engines, each dedicated to moving and transforming tabular data from main memory data to a subset of the core processors. Each data movement engine is coupled to an internal memory that stores data (e.g. a bit vector) that dictates how data manipulation operations are performed on tabular data moved from a main memory to the memories of a core processor, or to and from other memories. The internal memory of each data movement engine is private to the data movement engine.

Abstract: Example implementations relate to determining lengths of acknowledgment delays for input/output (I/O) commands. In example implementations, a length of an acknowledgment delay for a respective I/O command may be based on cache availability, and activity level of a drive at which the respective I/O command is directed, after the respective I/O command has been executed. Acknowledgments for respective I/O commands may be transmitted after respective periods of time equal to respective lengths of acknowledgment delays have elapsed.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.

Abstract: Disclosed is method for operating an interposer that includes assigning a binary port weight to a plurality of input ports of the interposer. The sum of all of the port weights is less than or equal to a number of traversals available to the interposer in a cycle. A traversal counter is set zero at the beginning of each cycle. The output of the traversal counter is a binary number of m bits. A mask is generated when a bit of the traversal counter transitions from a zero to a one. The mask is generated having the m?k+1 bit of the mask equal to one and all other bits of the mask equal to zero. Data is transmitted from each port when both the binary port weight and the mask have a one in the same bit position.

Abstract: The present disclosure provides an input device capable of communicating with other electronic devices, including a housing, a key module, a communication module and a message prompt module. The key module includes a plurality of keys disposed in the housing. The communication module transmits or receives at least a signal. The message prompt module prompts at least a message. The communication module receives a first signal, and the message prompt module prompts a first preset message corresponding to the first signal.

Abstract: A mobile computing device is provided. The device includes a first port having a pinout configuration that is configured to support at least one data format, a data source configured to provide data of a second data format that is different from the at least one data format, and a first multiplexer configured to selectively direct data from the data source towards the first port. The pinout configuration is modified to enable the first port to support the second data format.

Abstract: Methods and systems for allowing pilots and aircraft maintenance personnel to load data used by aircraft avionics (including but not limited to, Map Data, charts, XM Radio configuration data, LRU (line replaceable unit)/LRM (line replaceable module) specific configuration data or LRU/LRM software updates), wirelessly through the use of a USB to Wireless data bridge. The methods and systems can reduce and eliminate use of a USB (universal serial bus) hard drive or ‘keys’ be carried around with different collections of cockpit data.