Patents Examined by Kimberly N Rizkallah
  • Patent number: 11133568
    Abstract: A semiconductor package structure having an antenna module includes: a substrate, having a first surface, a second surface, and at least one via hole made by a laser running through the substrate; a rewiring layer, disposed on the first surface of the substrate; metal bumps, disposed on the rewiring layer and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole, and an antenna module, disposed on the second surface of the substrate and electrically connected to the metal bumps through the conductive column and the rewiring layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: September 28, 2021
    Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
    Inventors: Yenheng Chen, Chengtar Wu, Chengchung Lin
  • Patent number: 11127926
    Abstract: A method of manufacturing a display device having an organic EL device includes the steps of: forming an organic EL device over a substrate; and forming a protection film so as to cover the organic EL device. The protection film is made of a laminated film of a first insulating film containing Si, a second insulating film containing Al and a third insulating film containing Si. The step of forming the protection film includes the steps of: forming the first insulating film by a plasma CVD method so as to cover the organic EL device; forming the second insulating film over the first insulating film by an ALD method; and forming the third insulating film over the second insulating film by a plasma CVD method.
    Type: Grant
    Filed: November 27, 2016
    Date of Patent: September 21, 2021
    Assignee: THE JAPAN STEEL WORKS, LTD.
    Inventors: Keisuke Washio, Tatsuya Matsumoto, Junichi Shida, Takashi Ebisawa
  • Patent number: 11127648
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: September 21, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11094634
    Abstract: A semiconductor package structure and manufacturing method thereof are provided. The semiconductor package structure includes a package structure and a rigid-flexible substrate. The package structure includes semiconductor dies, a molding compound and a redistribution layer. The molding compound laterally encapsulates the semiconductor dies. The redistribution layer is disposed at a front side of the semiconductor dies and electrically connected to the semiconductor dies. The rigid-flexible substrate is disposed at a side of the redistribution layer opposite to the semiconductor dies, and includes rigid structures, a flexible core and a circuit layer. The rigid structures respectively have an interconnection structure therein. The interconnection structures are electrically connected to the redistribution layer. The flexible core laterally penetrates and connects the rigid structures.
    Type: Grant
    Filed: December 24, 2018
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuei-Tang Wang, Chen-Hua Yu, Chung-Shi Liu, Chih-Yuan Chang, Jiun-Yi Wu, Jeng-Shien Hsieh, Tin-Hao Kuo
  • Patent number: 11081418
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: August 3, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11069778
    Abstract: A method for producing a silicon carbide component includes forming a silicon carbide layer on an initial wafer, forming a doping region of the silicon carbide component to be produced in the silicon carbide layer, and forming an electrically conductive contact structure of the silicon carbide component to be produced on a surface of the silicon carbide layer. The electrically conductive contact structure electrically contacts the doping region. Furthermore, the method includes splitting the silicon carbide layer or the initial wafer after forming the electrically conductive contact structure, such that a silicon carbide substrate at least of the silicon carbide component to be produced is split off.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 20, 2021
    Assignee: Infineon Technologies AG
    Inventors: Roland Rupp, Ronny Kern
  • Patent number: 11049845
    Abstract: A semiconductor device comprises the following: a wiring substrate having on one side a recessed section and a plurality of connection pads; a first semiconductor chip mounted in the recessed section; a second semiconductor chip that has a plurality of electrode pads on the surface of at least one end section (in this case, both ends) and that is laminated onto the first semiconductor chip so that at least one end section (in this case, both ends) protrudes from the first semiconductor chip; a plurality of wires that mutually and electrically connect the plurality of connection pads of the wiring substrate and the plurality of electrode pads of the second semiconductor chip. One end section of the second semiconductor chip extends beyond the inner surface of the recessed section and is supported by one side of the wiring substrate.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: June 29, 2021
    Assignee: LONGITUDE LICENSING LIMITED
    Inventors: Takashi Ohba, Yoshihiro Sato
  • Patent number: 11043439
    Abstract: The present disclosure relates to a thermally enhanced package, which includes a carrier, a thinned die over the carrier, a mold compound, and a heat extractor. The thinned die includes a device layer over the carrier and a dielectric layer over the device layer. The mold compound resides over the carrier, surrounds the thinned die, and extends beyond a top surface of the thinned die to define an opening within the mold compound and over the thinned die. The top surface of the thinned die is at a bottom of the opening. At least a portion of the heat extractor is inserted into the opening and in thermal contact with the thinned die. Herein the heat extractor is formed of a metal or an alloy.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 22, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, George Maxim
  • Patent number: 11018040
    Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: May 25, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Roger St. Amand, Young Do Kweon
  • Patent number: 11004680
    Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: May 11, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Archana Venugopal, Benjamin Stassen Cook, Luigi Colombo, Robert Reid Doering
  • Patent number: 11004776
    Abstract: A semiconductor device may include a circuit board having an opening, and a frame. The frame may have an IC die pad in the opening, and arms extending outwardly from the IC die pad and coupled to the circuit board. The semiconductor device may include an IC mounted on the IC die pad, bond wires coupling the circuit board with the IC, and encapsulation material surrounding the IC, the bond wires, and the arms.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: May 11, 2021
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Jefferson Talledo, Rammil Seguido
  • Patent number: 10964627
    Abstract: Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heatsink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heatsink element. The heatsink element is formed by a heatsink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heatsink die towards the body and rest on the body.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: March 30, 2021
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Concetto Privitera, Maurizio Maria Ferrara, Fabio Vito Coppone
  • Patent number: 10944033
    Abstract: An optoelectronic component includes a radiation side, a contact side opposite a radiation side with at least two electrically conductive contact elements for external electrical contacting of the component, and a semiconductor layer sequence arranged between the radiation side and the contact side with an active layer that emits or absorbs electromagnetic radiation during normal operation, wherein the contact elements are spaced apart from each other at the contact side and are completely or partially exposed at the contact side in the unmounted state of the component, the region of the contact side between the contact elements is partially or completely covered with an electrically insulating, contiguously formed cooling element, the cooling element is in direct contact with the contact side and has a thermal conductivity of at least 30 W/(m·K), and in plan view of the contact side the cooling element covers one or both contact elements partially.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: March 9, 2021
    Assignee: OSRAM OLED GmbH
    Inventors: Luca Haiberger, David Racz, Matthias Sperl
  • Patent number: 10943863
    Abstract: Techniques for improving reliability in Cu interconnects using Cu intermetallics are provided. In one aspect, a method of forming a Cu interconnect in a dielectric over a Cu line includes the steps of: forming at least one via in the dielectric over the Cu line; depositing a metal layer onto the dielectric and lining the via such that the metal layer is in contact with the Cu line at the bottom of the via, wherein the metal layer comprises at least one metal that can react with Cu to form a Cu intermetallic; annealing the metal layer and the Cu line under conditions sufficient to form a Cu intermetallic barrier at the bottom of the via; and plating Cu into the via to form the Cu interconnect, wherein the Cu interconnect is separated from the Cu line by the Cu intermetallic barrier. A device structure is also provided.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: March 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Chao-Kun Hu, Christian Lavoie, Stephen M. Rossnagel, Thomas M. Shaw
  • Patent number: 10937981
    Abstract: A light-emitting element is provided, including a first electrode and a second electrode, a first layer including first and second organic compounds, the first layer being formed between the first electrode and the second electrode wherein the first organic compound is capable of emitting a first light and the second organic compound has an electron transporting property, and a second layer including third and fourth organic compounds, the second layer being formed between the first layer and the second electrode wherein the third organic compound is capable of emitting a second light and has an electron trap property and the fourth organic compound has an electron transporting property.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: March 2, 2021
    Inventors: Tsunenori Suzuki, Satoshi Seo
  • Patent number: 10930636
    Abstract: A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: February 23, 2021
    Assignee: Amazing Microelectronic Corp.
    Inventors: Kun-Hsien Lin, Zi-Ping Chen, Che-Hao Chuang
  • Patent number: 10916829
    Abstract: A semiconductor package structure having an antenna module includes: a substrate, having at least one via hole running through the substrate; a rewiring layer, disposed on a surface of the substrate; a metal bump, disposed on and electrically connected to the rewiring layer; a semiconductor chip, disposed on and electrically connected to the rewiring layer; a conductive column, filling the via hole; a plastic packaging material layer, surrounding the metal bump and the semiconductor chip; and an antenna module, electrically connected to the metal bump through the conductive column and the rewiring layer.
    Type: Grant
    Filed: December 26, 2018
    Date of Patent: February 9, 2021
    Assignee: SJ Semiconductor (Jiangyin) Corporation
    Inventors: Yenheng Chen, Chengtar Wu, Chengchung Lin
  • Patent number: 10910298
    Abstract: An electronic package includes a substrate having a plurality of lands embedded within an insulating layer. Conductive patterns are disposed on at least a portion of a respective land top surface. An electronic device is electrically connected to the conductive patterns, wherein the land bottom surfaces are exposed to the outside. In another embodiment, the top land surfaces and the top surface of the insulating layer are substantially co-planar and the conductive patterns further overlap portions of the top surface of the insulating layer. In one embodiment, a package body encapsulates the top surface of the insulating material and the electronic device, wherein the land bottom surfaces are exposed to the outside of the package body.
    Type: Grant
    Filed: February 3, 2018
    Date of Patent: February 2, 2021
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Won Bae Bang, Byong Jin Kim, Gi Jeong Kim, Ji Young Chung
  • Patent number: 10867850
    Abstract: A method for forming a semiconductor structure is provided. A substrate including a metal portion and a low-k dielectric portion formed thereon is provided. The metal portion adjoins the low-k dielectric portion. A SAM solution is prepared. The SAM solution includes at least one blocking compound and a multi-solvent system. The multi-solvent system includes an alcohol and an ester. The SAM solution is applied over surfaces of the metal portion and the low-k dielectric portion. The substrate is heated to remove the multi-solvent system of the SAM solution to form a blocking layer on one of the metal portion and the low-k dielectric portion. A material layer is selectively deposited on the other one of the metal portion and the low-k dielectric portion using the blocking layer as a stencil. The blocking layer is removed from the substrate.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Chin Lee, Shao-Kuan Lee, Hsin-Yen Huang, Hai-Ching Chen, Shau-Lin Shue
  • Patent number: 10867958
    Abstract: An integrated circuit includes a substrate and at least one chip. Each chip is disposed over the substrate or the other chip. Solder bumps are disposed between the substrate and the at least one chip. An insulating film is disposed around the solder bumps and provides electrical insulation for the solder bumps except areas for interconnections. A thermally conductive underfill is disposed between the substrate, the at least one chip, and the solder bumps.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Tien-I Bao