Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

Abstract: A SiC ohmic contact preparation method is provided and includes: selecting a SiC substrate; preparing a graphene/SiC structure by forming a graphene on a Si-face of the SiC substrate; depositing an Au film on the graphene of the graphene/SiC structure; forming a first transfer electrode pattern on the Au film by a first photolithography; etching the Au film uncovered by the first transfer electrode pattern through a wet etching; etching the graphene uncovered by the Au film through a plasma etching after the wet etching; forming a second transfer electrode pattern on the SiC substrate by a second photolithography; depositing an Au material on the Au film exposed by the second transfer electrode pattern and forming an Au electrode and then annealing. The graphene reduces potential barrier associated with the SiC interface, specific contact resistance of ohmic contact reaches the order of 10?7˜10?8 ?·cm2, and the method has high repeatability.

Abstract: A molded semiconductor package includes: a semiconductor die embedded in a mold compound; a first heat spreader partly embedded in the mold compound and thermally coupled to a first side of the semiconductor die; and a second heat spreader partly embedded in the mold compound and thermally coupled to a second side of the semiconductor die opposite the first side. The first heat spreader includes at least one heat dissipative structure protruding from a side of the first heat spreader uncovered by the mold compound and facing away from the semiconductor die. The mold compound is configured to channel a fluid over the at least one heat dissipative structure in a direction parallel to the first side of the power semiconductor die. Corresponding methods of production and electronic assemblies are also described.

Abstract: In an embodiment, a Group III nitride-based transistor device includes a source electrode, a drain electrode and a gate electrode positioned on a first major surface of a Group III nitride based-based layer, wherein the gate electrode is laterally arranged between the source electrode and the drain electrode, a passivation layer arranged on the first major surface and a field plate coupled to the source electrode, the field plate having a lower surface arranged on the passivation layer. The field plate is laterally arranged between and laterally spaced apart from the gate electrode and the drain electrode.

Abstract: Apparatus and methods for generating a physical layout for a high density routing circuit are disclosed. An exemplary semiconductor structure includes: a gate structure; a plurality of first metal lines formed in a first dielectric layer below the gate structure; at least one first via formed in a second dielectric layer between the gate structure and the first dielectric layer; a plurality of second metal lines formed in a third dielectric layer over the gate structure; and at least one second via formed in a fourth dielectric layer between the gate structure and the third dielectric layer. Each of the at least one first via is electrically connected to the gate structure and a corresponding one of the plurality of first metal lines. Each of the at least one second via is electrically connected to the gate structure and a corresponding one of the plurality of second metal lines.

Abstract: A method of processing a substrate includes forming a first layer stack on a substrate, the first layer stack including conductive layers and dielectric layers that alternate in the first layer stack. An opening is formed in the first layer stack, the opening extending through each of the conductive layers in the first layer stack such that sidewalls of each of the conductive layers are exposed within the opening. A second stack of layers is formed within the opening, the second stack of layers including channel layers of semiconductor material positioned in the second stack such that each channel layer contacts exposed sidewalls of a respective conductive layer of the first layer stack. Transistor channels are from the channel layers of the second stack such that each transistor channel extends between exposed sidewalls of a respective conductive layer within the opening.

Abstract: The present disclosure is drawn to thin-film transistors, electronic displays that include thin-film transistors, and methods of making thin-film transistors. In one example, a thin-film transistor can include a nonconductive substrate, a semiconductor layer on the nonconductive substrate, a source electrode adjacent a first side of the semiconductor layer and partially overlapping a first peripheral portion of the semiconductor layer, a drain electrode adjacent a second side of the semiconductor layer and partially overlapping a second peripheral portion of the semiconductor layer, an etch stop layer on the semiconductor layer, a gat insulator layer on the etch stop layer, and a gate electrode on the gate insulator layer. The source electrode and the drain electrode do not overlap the etch stop layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located within the memory openings. Each of the electrically conductive layers includes a metallic fill material layer and a plurality of vertical tubular metallic liners laterally surrounding a respective one of the memory opening fill structures and located between the metallic fill material layer and a respective one of the memory opening fill structures. The tubular metallic liners may be formed by selective metal or metal oxide deposition, or by conversion of surface portions of the metallic fill material layers into metallic compound material portions by nitridation, oxidation, or incorporation of boron atoms.

Abstract: A semiconductor device includes: an oscillator including external terminals disposed on a first face with a specific distance along a first direction; an integrated circuit including a first region formed with first electrode pads along one side, and a second region formed with second electrode pads on two opposing sides of the first region; a lead frame that includes terminals at a peripheral portion, and on which the oscillator and the integrated circuit are mounted such that the external terminals, the first and second electrode pads face in a substantially same direction and such that one side of the integrated circuit is substantially parallel to the first direction; a first bonding wire that connects one external terminal to one first electrode pad; a second bonding wire that connects one terminal of one lead frame to one second electrode pad; and a sealing member that seals all of the components.

Abstract: An image sensor is fabricated by first heavily p-type doping the thin top monocrystalline silicon substrate of an SOI wafer, then forming a relatively lightly p-doped epitaxial layer on a top surface of the top silicon substrate, where p-type doping levels during these two processes are controlled to produce a p-type dopant concentration gradient in the top silicon substrate. Sensing (circuit) elements and associated metal interconnects are fabricated on the epitaxial layer, then the handling substrate and oxide layer of the SOI wafer are at least partially removed to expose a lower surface of either the top silicon substrate or the epitaxial layer, and then a pure boron layer is formed on the exposed lower surface. The p-type dopant concentration gradient monotonically decreases from a maximum level near the top-silicon/epitaxial-layer interface to a minimum concentration level at the epitaxial layer's upper surface.

Abstract: A package is disclosed. In one example, the package comprises a carrier, a semiconductor chip having a first connection area at which the semiconductor chip is mounted at a first vertical level on or above the carrier, and a connection body. The semiconductor chip is bent to thereby be connected at a second connection area of the semiconductor chip at a second vertical level, being different from the first vertical level, with the connection body.

Abstract: Wafer-level packaging of solid-state transducers (“SSTs”) is disclosed herein. A method in accordance with a particular embodiment includes forming a transducer structure having a first surface and a second surface opposite the first surface, and forming a plurality of separators that extend from at least the first surface of the transducer structure to beyond the second surface. The separators can demarcate lateral dimensions of individual SSTs. The method can further include forming a support substrate on the first surface of the transducer structure, and forming a plurality of discrete optical elements on the second surface of the transducer structure. The separators can form barriers between the discrete optical elements. The method can still further include dicing the SSTs along the separators. Associated SST devices and systems are also disclosed herein.

Abstract: An image sensor including a substrate having first and second surfaces that are opposite to each other. The substrate includes unit pixel regions having photoelectric conversion regions. A semiconductor pattern is disposed in a first trench defined in the substrate and defines the unit pixel regions. The semiconductor pattern includes a first semiconductor pattern and a second semiconductor pattern disposed on the first semiconductor pattern. A back-side insulating layer covers the second surface of the substrate. The first semiconductor pattern includes a side portion extended along an inner side surface of the first trench and a bottom portion connected to the side portion and disposed closer to the second surface of the substrate than the side portion. The second semiconductor pattern extends toward the second surface of the substrate and is spaced apart from the back-side insulating layer with the bottom portion of the first semiconductor pattern interposed therebetween.

Abstract: An image sensor may include a substrate having first and second surfaces opposite to each other and including unit pixel regions and impurity regions near the first surface, a device isolation pattern provided on the first surface to define the impurity regions, and an interconnection layer including an insulating layer covering the first surface of the substrate, interconnection lines on the insulating layer, and a penetration structure penetrating the insulating layer. The penetration structure may include a first pattern connected to one of the impurity regions and in contact with at least a portion of the device isolation pattern, a second pattern provided on the first pattern and in contact with the interconnection lines, and a third pattern provided between the first and second patterns. A top surface of the first pattern may be higher than that of the device isolation pattern.

Abstract: For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.

Abstract: There is provided a technique that includes: forming a film containing Si, O and N or a film containing Si and O on a substrate by performing a cycle a predetermined number of times under a condition where SiCl4 is not gas-phase decomposed, the cycle including non-simultaneously performing: (a) forming NH termination on a surface of the substrate by supplying a first reactant containing N and H to the substrate; (b) forming a SiN layer having SiCl termination formed on its surface by supplying the SiCl4 as a precursor to the substrate to react the NH termination formed on the surface of the substrate with the SiCl4; and (c) reacting the SiN layer having the SiCl termination with a second reactant containing O by supplying the second reactant to the substrate.

Abstract: An isolated power converter package includes a leadframe including a first and second die pad, first and second supports connected to first leads, second leads, at least one downset pad, and at least one downset feature between the supports and downset pad. A first semiconductor die is on the first die pad and a second semiconductor die is on the second die pad. The transformer stack includes a top and bottom side magnetic sheet on respective sides of a laminate substrate including an embedded coil that has coil contacts. Edges of the laminate substrate are on the supports. Bond wires are between the first die bond pads and the second leads, between the second die bond pads and the second leads, between the first die bond pads and coil contacts, and between the second die bond pads and the coil contacts. The downset pad is exposed from a mold compound.

Abstract: A semiconductor die comprises: a first semiconductor device and a second semiconductor device. The first semiconductor device comprises a first device portion comprising a first sub-array of memory devices, and a first interface portion located adjacent to the first device portion in a first direction. The first interface portion has a staircase profile in a vertical direction. The second semiconductor device comprises a second device portion adjacent to the first device portion in the first direction opposite the first interface portion. The second device portion comprises a second sub-array of memory devices, and a second interface portion located adjacent to the first device portion in the first direction opposite the first interface portion. The second interface portion also has a staircase profile in the vertical direction. The first semiconductor device is electrically isolated from the second semiconductor device.

Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.

Abstract: A method for forming a semiconductor device includes providing a to-be-etched layer, forming a first mask layer on the to-be-etched layer, forming a patterned core layer on the first mask layer of a first region, forming a sidewall spacer material layer on the core layer and the first mask layer, removing the sidewall spacer material layer on a top surface of the core layer, removing the core layer and the first mask layer at a bottom of the core layer to form a first trench, removing the sidewall spacer material layer on the first mask layer of a second region, forming a first patterned layer exposing the first mask layer of the second region, and using the first patterned layer as a mask to remove the first mask layer of the second region to form a second trench.