Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.

Abstract: The light-emitting device according to one embodiment includes a substrate; a plurality of light-emitting cells disposed on the substrate so as to be spaced apart from each other; and a connection line configured to electrically interconnect neighboring light-emitting cells, wherein each of the light-emitting cells includes: a light-emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer disposed on the substrate; and first and second electrodes configured to be electrically connected to the first and second semiconductor layers respectively, wherein the light-emitting cells include: a first power cell configured to receive first power via the first electrode; and a second power cell configured to receive second power via the second electrode, and wherein the first electrode in the first power cell has a first planar shape different from a second planar shape of the second electrode in the second power cell.

Abstract: Transistors might include first and second semiconductor fins, a first source/drain region in the first semiconductor fin and extending downward from an uppermost surface of the first semiconductor fin, a second source/drain region in the second semiconductor fin and extending downward from an uppermost surface of the second semiconductor fin, a dielectric between the first and second semiconductor fins and adjacent to sidewalls of the first and second semiconductor fins, and a control gate over the dielectric and between the first and second semiconductor fins and extending to a level below upper surfaces of the first and second source/drain regions.

Abstract: A method for manufacturing a bonded SOI wafer, including depositing a polycrystalline silicon layer on a base wafer, forming an insulator film on a bond wafer, bonding the bond wafer and a polished surface of the silicon layer with the insulator film interposed, and thinning the bond wafer, wherein a silicon single crystal wafer having a resistivity of 100 ?·cm or more is the base wafer, the step of depositing the silicon layer includes a stage of forming an oxide film on the surface of the base wafer, and the silicon layer is deposited between 1050° C. and 1200° C. Accordingly, the method enables a polycrystalline silicon layer to be deposited while preventing the progress of single crystallization even through a heat treatment step in the SOI wafer manufacturing process or a heat treatment step in the device manufacturing process and can improve throughput in the polycrystalline silicon layer depositing step.

Abstract: Provided is a method of fabricating an image sensor device. An exemplary includes forming a plurality of radiation-sensing regions in a substrate. The substrate has a front surface, a back surface, and a sidewall that extends from the front surface to the back surface. The exemplary method further includes forming an interconnect structure over the front surface of the substrate, removing a portion of the substrate to expose a metal interconnect layer of the interconnect structure, and forming a bonding pad on the interconnect structure in a manner so that the bonding pad is electrically coupled to the exposed metal interconnect layer and separated from the sidewall of the substrate.

Abstract: A method for semiconductor device fabrication includes forming storage elements on conductive structures. A cap layer is deposited over the storage elements and the conductive structures. An interlevel dielectric (ILD) layer is formed over the cap layer. Trenches are patterned in the ILD layer to expose a top portion of the storage elements. The storage elements where interlevel vias are to be formed is removed to expose the conductive structures therebelow to form via openings. A conductive material is deposited in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.

Abstract: A substrate includes a substrate body including a plurality of chip mounting regions and a peripheral region surrounding the plurality of chip mounting regions, each of the chip mounting regions including a conductive plane. The substrate further includes a conductive support structure located in the peripheral region, first conductive lines connected between the conductive planes of adjacent chip mounting regions, and second conductive lines connected between the conductive support structure and the conductive planes of chip mounting regions located adjacent the peripheral region.

Abstract: A light source device includes an electronic component and a substrate. The electronic component includes first and second electrodes exposed at a lower surface. The first electrode includes first and second parts separated from each other by a separation region on the lower surface of the electronic component. The substrate includes a basal member and a first and second wiring layers disposed on an upper surface of the basal member. The electronic component is mounted to the substrate so that upper surfaces of the first and second wiring layers respectively face the first and second electrodes. The substrate includes a first region at a position overlapping the separation region as seen in a top view. Solder wettability of the substrate in the first region is lower than solder wettability of the substrate in at least regions of the first wiring layer facing the first and second parts of the first electrode.

Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Abstract: At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or metallic contact region) is provided to each of the openings. The void-free metallization region has the biconvex shape and exhibits a low wire resistance.

Abstract: An integrated circuit structure includes a semiconductor substrate, and a dielectric pad extending from a bottom surface of the semiconductor substrate up into the semiconductor substrate. A low-k dielectric layer is disposed underlying the semiconductor substrate. A first non-low-k dielectric layer is underlying the low-k dielectric layer. A metal pad is underlying the first non-low-k dielectric layer. A second non-low-k dielectric layer is underlying the metal pad. An opening extends from a top surface of the semiconductor substrate down to penetrate through the semiconductor substrate, the dielectric pad, and the low-k dielectric layer, wherein the opening lands on a top surface of the metal pad. A passivation layer includes a portion on a sidewall of the opening, wherein a portion of the passivation layer at a bottom of the opening is removed.

Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.

Abstract: A metal hard mask layer is deposited on a MTJ stack on a substrate. A hybrid hard mask is formed on the metal hard mask layer, comprising a plurality of spin-on carbon layers alternating with a plurality of spin-on silicon layers wherein a topmost layer of the hybrid hard mask is a silicon layer. A photo resist pattern is formed on the hybrid hard mask. First, the topmost silicon layer of the hybrid hard mask is etched where is it not covered by the photo resist pattern using a first etching chemistry. Second, the hybrid hard mask is etched where it is not covered by the photo resist pattern wherein the photoresist pattern is etched away using a second etch chemistry. Thereafter, the metal hard mask and MTJ stack are etched where they are not covered by the hybrid hard mask to form a MTJ device and overlying top electrode.

Abstract: A silicon carbide semiconductor device includes: n type regions formed on a surface of the n? type epitaxial layer; p type body regions formed at positions deeper than the n type regions; p? type channel regions each reaching the p type body region; and n++ type source regions formed toward the p type body region from the front surface side of the epitaxial layer, and the p? type channel regions and the n++ type source regions are formed at a planar position where the n type region remains between the p? type channel region and the n++ type source region, and out of boundary surfaces which are formed between the p? type channel region and the n type regions, the boundary surface on an outer peripheral side is positioned inside an outer peripheral surface 116a of the p type body region as viewed in a plan view.

Abstract: A semiconductor device has a bonding pad and a wiring layer formed on an insulating film. The wiring layer is spaced from the bonding pad by a gap. A passivation film covers the bonding pad and the wiring layer and fills the gap. The gap has a width equal to or larger than the thickness of the passivation film, and equal to or smaller than twice a side wall thickness of the passivation film covering a side wall of the wiring layer. The semiconductor device has a high resistance to stress during bonding.

Abstract: A QFP has a die pad on which a semiconductor chip is mounted, a plurality of inner parts disposed around the die pad, a plurality of outer parts respectively connected with the plurality of inner parts, a plurality of wires electrically connect the bonding pads of the semiconductor chip and the plurality of inner parts, and a sealing body that seals the semiconductor chip. Moreover, the thickness of the semiconductor chip is larger than a thickness from a lower surface of the die pad to a lower surface of the sealing body, and a distance from the lower surface of the sealing body to a tip portion of each of the plurality of outer parts is larger than a thickness of the sealing body from a main surface of the semiconductor chip to an upper surface of the sealing body.

Abstract: Methods and systems for using the downstream active residuals of a reducing-chemistry atmospheric plasma to provide multiple advantages to pre-plating surface preparation with a simple apparatus. As the downstream active species of the atmospheric plasma impinge the substrate surface, three important surface preparation processes can be performed simultaneously: 1. Organic residue is removed from the surface of the plating base. 2. Oxidation is removed from the surface of the plating base. 3. All surfaces on the substrate are highly activated by the downstream active residuals thus creating a highly wettable surface for subsequent plating operations.

Abstract: The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking alignment and a multi-chip semiconductor device employing thereof, and to a method for manufacturing same. In some embodiments, the semiconductor chip includes a semiconductor substrate having a first side and a second side, a conductive through plug extending through the semiconductor substrate from the first side to the second side, and a plurality of non-through plugs extending through the semiconductor substrate from the first side to the second side.

Abstract: According to one embodiment, a method includes forming a drain contact above a channel, each having a hollow circular cross-section thereof along a plane perpendicular to a film thickness direction, forming gate dielectric layers on sides of the drain contact and the channel, forming a source line positioned below the channel that is electrically coupled to a plurality of channels in a direction along the plane, forming gate layers on sides of the gate dielectric layers, where an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane, and where an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane, forming an electrode above the upper surface of the drain contact, and forming a fourth insulative layer on sides of the electrode along the plane.

Abstract: An embodiment comprises: a substrate having a chip mounting region; first and second wiring layers disposed on the substrate around the chip mounting region so as to be spaced apart from each other; and a plurality of light emitting chips disposed on the chip mounting region, wherein the first wiring layer comprises a first wiring pattern disposed at one side of a reference line and having a first concave part, and a first extending pattern extending from the first wiring pattern to the other side of the reference line, the second wiring layer comprises a second wiring pattern disposed at the other side of the reference line and having a second concave part, and a second extending pattern extending from the second wiring pattern to one side of the reference line, and the reference line is a straight line passing through the center of the chip mounting region.