Abstract: An etching apparatus is provided, in which a plurality of electrodes are disposed for placing a substrate, high-frequency power sources as many as electrodes are provided, and the electrodes and the high-frequency power sources are connected to each other independently. Among a plurality of electrodes, a high-frequency power applied to an electrode disposed below the central portion of the substrate and a high-frequency power applied to electrodes disposed below comer portions of the substrate are controlled respectively, whereby in-plane uniformity of etching can be enhanced.

Abstract: A method and apparatus for the formation of oxide in a manner having a planarizing effect on underlying material, e.g., silicon. In particular, an oxide having a nonuniform thickness profile is grown on the underlying material. The nonuniform thickness profile of the oxide is selected according to the nonuniform profile of the underlying material. Subsequent removal of the oxide leaves behind a planarized surface of the underlying material, as compared to the pre-oxidized surface.

Abstract: Damage to the rim of a semiconductor wafer caused by etching processes is reduced by forming a rim of photoresist or other material around the outer edge of the wafer that has a thickness such that images projected on the rim are sufficiently out of focus that they do not develop, so that etching takes place only in the interior.

Abstract: One aspect of the present invention relates to a system and method for controlling defect formation during a resist strip process. The system includes a reaction chamber comprising a patterned resist layer overlying a semiconductor structure wherein the resist layer is being exposed to a plasma material flowing into the chamber in order to facilitate removing the resist layer from the structure, a plasma-resist particle monitoring system connected to the reaction chamber and programmed to determine a particle count in the reaction chamber during the resist strip process, and a reaction controller coupled to the chamber and to the monitoring system, the reaction controller being programmed to receive particle data from the monitoring system to facilitate determining whether the counted particles in the chamber are within a tolerable limit. The method involves continuing to expose the structure and the chamber to the plasma until an acceptable particle count is obtained.

Abstract: In a plasma treating apparatus for carrying out a plasma treatment over a silicon wafer 6 having a protective tape 6a stuck to a circuit formation face, the silicon wafer 6 is mounted on a mounting surface 3d which is provided on an upper surface of a lower electrode 3 formed of a conductive metal with the protective tape 6a turned toward the mounting surface 3d. When a DC voltage is to be applied to the lower electrode 3 by a DC power portion 18 for electrostatic adsorption to adsorb and hold the silicon wafer 6 onto the lower electrode 3 in the plasma treatment, the protective tape 6a is utilized as a dielectric for the electrostatic adsorption. Consequently, the dielectric can be thinned as much as possible and the silicon wafer 6 can be held by a sufficient electrostatic holding force.

Abstract: A method and apparatus for the formation of oxide in a manner having a planarizing effect on underlying material, e.g., silicon. In particular, an oxide having a nonuniform thickness profile is grown on the underlying material. The nonuniform thickness profile of the oxide is selected according to the nonuniform profile of the underlying material. Subsequent removal of the oxide leaves behind a planarized surface of the underlying material, as compared to the pre-oxidized surface.

Abstract: A method of making a semiconductor device, comprises preparing a plurality of lots each including semiconductor substrates to be processed, the plurality of lots including at least first and second lots, processing the plurality of lots for every one lot, using a semiconductor manufacturing apparatus, judging whether or not the semiconductor manufacturing apparatus is subjected to cleaning before the second lot is processed, depending upon both a first processing type of the first lot to be processed and a second processing type of the second lot to be processed after the first lot, and processing the second lot without the cleaning in the case where the second lot does not require the cleaning.

Abstract: First and second pressure sensors 132 and 134 that perform pressure detection over different pressure detection ranges from each other detect the pressure within a process chamber 102 of an etching device 100. A pressure controller 144 selects optimal pressure data in correspondence to the pressure inside the process chamber from the pressure data provided by the first and second pressure sensors 132 and 134. It also analyzes the selected pressure data at a resolution selected in correspondence to the pressure inside the process chamber 102 and thus obtains pressure data achieving a predetermined data density. The pressure controller 134 controls a pressure control valve 130 so as to ensure that the pressure data match preset pressure data.

Abstract: A method for cleaning substrates to remove Group VIII metal-containing, particularly platinum-containing, residue using a cleaning composition that includes a peroxide-generating compound.

Abstract: Methods and apparatuses for planarizing microelectronic substrate assemblies on fixed-abrasive polishing pads with non-abrasive lubricating planarizing solutions. One aspect of the invention is to deposit a lubricating planarizing solution without abrasive particles onto a fixed-abrasive polishing pad having a body, a planarizing surface on the body, and a plurality of abrasive particles fixedly attached to the body at the planarizing surface. The front face of a substrate assembly is pressed against the lubricating planarizing solution and at least a portion of the fixed abrasive particles on the planarizing surface of the polishing pad. At least one of the polishing pad or the substrate assembly is then moved with respect to the other to impart relative motion therebetween. As the substrate assembly moves relative to the polishing pad, regions of the front face are separated from the abrasive particles in the polishing pad by a lubricant-additive in the lubricating planarizing solution.

Abstract: A method for operating a plasma reactor to etch high-aspect-ratio features on a workpiece in a vacuum chamber. The method comprises the performance of an etch process followed by a flash process. During the etch process, a first gas is supplied into the vacuum chamber, and a plasma of the first gas is maintained for a first period of time. The plasma of the first gas comprises etchant and passivant species. During the flash process, a second gas comprising a deposit removal gas is supplied into the vacuum chamber, and a plasma of the second gas is maintained for a second period of time. The DC voltage between the workpiece and the plasma of the second gas during the second period of time is significantly less than the DC voltage between the workpiece and the plasma of the first gas during the first period of time.

Abstract: Novel aqueous, acid etch solutions comprising a fluorinated surfactant are provided. The etch solutions are used with a wide variety of substrates, for example, in the etching of silicon oxide-containing substrates.

Abstract: A method for improving a photolithographic patterning process to avoid undeveloped photoresist contamination in a semiconductor manufacturing process including providing a first semiconductor feature having an anisotropically etched opening including sidewalls. The first semiconductor feature further provide an overlying photoresist layer photolithographically patterned for anisotropically etching a second semiconductor feature opening overlying and encompassing the first semiconductor feature; blanket depositing a polymeric passivation layer over the overlying photoresist layer including covering at least a portion of the sidewalls including polymeric containing residues; and, removing the polymeric passivation layer including a substantial portion of the polymeric containing residues from at least a portion of the sidewalls prior to anisotropically etching the second semiconductor feature.

Abstract: A method for handling a thin silicon wafer including the steps of successively forming on a surface of the wafer a first protection layer, a first etch stop layer, and an external layer; forming on a surface of a support wafer a gluing layer of the same material as the external layer of the wafer, the surface of the support wafer including a plurality of pads, the respective upper portions of which are substantially planar and coplanar; fastening, by direct gluing, the external layer of the wafer and the gluing layer of the support wafer; processing the wafer to form circuits therein; depositing a second protection layer on the wafer surface which is not glued to the support wafer; and removing by an etch process the material forming the external layer of the wafer and the gluing layer of the support wafer.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate electrodes on a semiconductor substrate, forming an etching prevention film over the surface of the adjacent gate electrodes and on the semiconductor substrate between the adjacent gate electrodes, and forming an organic insulation film having heat-resistance on the etching prevention film. The method further includes removing the organic insulation film above the gate electrodes in such a manner that the organic insulation film remains between the gate electrodes, forming an interlayer insulation film on a laminate section obtained by the organic insulation film removing step, forming a contact hole by removing the interlayer insulation film on the remaining organic insulation film with a width wider than the distance between the gate electrodes, and exposing the semiconductor substrate between the gate electrodes by removing the organic insulation film and the etching prevention film remaining inside the contact hole.

Abstract: A slurry for use in polishing a first material having a first hardness, wherein the first material overlies a second material having a second hardness, and the second hardness is greater than the first hardness, includes an abrasive that has a hardness which is greater than that of the first material but less than that of the second material. In a particular embodiment of the present invention copper overlying a copper diffusion barrier is polished with a slurry having an abrasive which is harder than copper but less hard than the copper diffusion barrier. Iron oxide, strontium titanate, apatite, dioptase, iron, brass, fluorite, hydrated iron oxide, and azurite, are examples of materials that are harder than copper but less hard than materials typically used as copper diffusion barriers in integrated circuits.

Abstract: A structure and method for achieving a flip-chip semiconductor device having plated copper inductors (4), transformers (16), interconnect, and power busing that is electrically superior, lower cost, and provides for higher quality inductors as well as lower losses for on-chip transformers. Providing a solder dam (8, 24, 28) enables the fabrication of flip-chip solder bumps directly on to inductors and transformers.

Abstract: A semiconductor device capable of suppressing diffusion of copper at an interface between a copper wire and a cap film to enhance an electromigration resistance to ensure reliability of the copper wire, and a manufacturing method thereof are provided. The semiconductor device according to the present invention comprises an insulating film (12) formed on a substrate (11), a concave portion (13) (for example, a groove) formed in the insulating film, a conductive layer (15) embedded in the concave portion through a barrier layer (14), and a cobalt tungsten phosphorus coating (16) to connect with the barrier layer on the side of the conductive layer and to coat the conductive layer on the opening side of the concave portion.

Abstract: An etchant including C2HxFy, where x is an integer from two to five, inclusive, where y is an integer from one to four, inclusive, and where x plus y equals six etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

Abstract: A master wafer is replicated by creating a mold by plating a nickel electroform on a surface of a silicon wafer. Thereafter, a child wafer is prepared with a layer of photoresist or similar material that is compatible with plasma-etching techniques. Thereafter, the mold shape is transferred to the photoresist through compression molding, thereafter the child wafer is etched.